LTC1850/LTC1851
8-Channel, 10-Bit/12-Bit,
1.25Msps Sampling ADCs
DESCRIPTIO
The 10-bit LTC
®
1850 and 12-bit LTC1851 are complete
8-channel data acquisition systems. They include a flex-
ible 8-channel multiplexer, a 1.25Msps successive approxi-
mation analog-to-digital converter with sample-and-hold,
an internal 2.5V reference and reference buffer amplifier,
and a parallel output interface. The multiplexer can be con-
figured for single-ended or differential inputs, two gain
ranges and unipolar or bipolar operation.
The ADCs have a scan mode that will repeatedly cycle
through all 8 multiplexer channels and can also be
programmed with a sequence of up to 16 addresses and
configurations that can be scanned in succession. The
sequence memory can also be read back. The reference
and buffer amplifier provide pin strappable ranges of
4.096V, 2.5V and 2.048V. The parallel output includes
the 10-bit or 12-bit conversion result plus the 4-bit
multiplexer address. The digital outputs are powered
from a separate supply allowing for easy interface to 3V
digital logic. Typical power consumption is 40mW at
1.25Msps from a single 5V supply.
, LTC and LT are registered trademarks of Linear Technology Corporation.
FEATURES
s
s
s
s
s
s
s
s
s
s
s
s
Flexible 8-Channel Multiplexer
Single-Ended or Differential Inputs
Two Gain Ranges Plus Unipolar and Bipolar
Operation
1.25Msps Sampling Rate
Single 5V Supply and 40mW Power Dissipation
Scan Mode and Programmable Sequencer
Pin Compatible 10-Bit LTC1850 and 12-Bit LTC1851
True Differential Inputs Reject Common Mode Noise
Internal 2.5V Reference
Parallel Output Includes MUX Address
Easy Interface to 3V Logic
Nap and Sleep Shutdown Modes
APPLICATIO S
s
s
s
s
s
s
High Speed Data Acquisition
Test and Measurement
Imaging Systems
Telecommunications
Industrial Process Control
Spectrum Analysis
BLOCK DIAGRA
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
2.5V
REFERENCE
8-CHANNEL
MULTIPLEXER
LTC1851
CONTROL LOGIC
AND
PROGRAMMABLE
SEQUENCER
INTERNAL
CLOCK
OV
DD
BUSY
DIFF
OUT
/S6
A2
OUT
/S5
A1
OUT
/S4
A0
OUT
/S3
D11/S2
D10/S1
D9/S0
D8
D7
D6
D5
D4
D3
D2
D1
D0
OGND
1851 BD
INL COC ERROR (LSBs)
M1
SHDN
CS
CONVST
RD
WR
DIFF
A2
A1
A0
UNI/BIP
PGA
M0
REFOUT
12-BIT
1.25Msps ADC
DATA
LATCHES
OUTPUT
DRIVERS
REFIN
REF AMP
REFCOMP
U
W
U
Integral Linearity, LTC1851
1.00
0.50
0.00
–0.50
–1.00
0
512 1024 1536 2048 2560 3072 3584 4096
CODE
LTC1850/51 G01
18501f
1
LTC1850/LTC1851
ABSOLUTE
AXI U
RATI GS
Supply Voltage (V
DD
) ................................................. 6V
Analog Input Voltage (Note 3) ..... – 0.3V to (V
DD
+ 0.3V)
Digital Input Voltage (Note 4) ....................– 0.3V to 10V
Digital Output Voltage .................. – 0.3V to (V
DD
+ 0.3V)
Power Dissipation .............................................. 500mW
PACKAGE/ORDER I FOR ATIO
TOP VIEW
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
1
2
3
4
5
6
7
8
9
48 M1
47 SHDN
46 CS
45 CONVST
44 RD
43 WR
42 DIFF
41 A2
40 A1
39 A0
38 UNI/BIP
37 PGA
36 M0
35 OV
DD
34 OGND
33 BUSY
32 NC
31 NC
30 D0
29 D1
28 D2
27 D3
26 D4
25 D5
ORDER PART
NUMBER
LTC1850CFW
LTC1850IFW
REFOUT 10
REFIN 11
REFCOMP 12
GND 13
V
DD
14
V
DD
15
GND 16
DIFF
OUT
/S6 17
A2
OUT
/S5 18
A1
OUT
/S4 19
A0
OUT
/S3 20
D9/S2 21
D8/S1 22
D7/S0 23
D6 24
FW PACKAGE
48-LEAD PLASTIC TSSOP
T
JMAX
= 150°C,
θ
JA
= 110°C/W
Consult LTC Marketing for parts specified with wider operating temperature ranges.
2
U
U
W
W W
U
W
OV
DD
= V
DD
(Notes 1, 2)
Ambient Operating Temperature Range
LTC1850C/LTC1851C ............................ 0°C to 70°C
LTC1850I/LTC1851I .......................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................ 300°C
TOP VIEW
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
1
2
3
4
5
6
7
8
9
48 M1
47 SHDN
46 CS
45 CONVST
44 RD
43 WR
42 DIFF
41 A2
40 A1
39 A0
38 UNI/BIP
37 PGA
36 M0
35 OV
DD
34 OGND
33 BUSY
32 D0
31 D1
30 D2
29 D3
28 D4
27 D5
26 D6
25 D7
ORDER PART
NUMBER
LTC1851CFW
LTC1851IFW
REFOUT 10
REFIN 11
REFCOMP 12
GND 13
V
DD
14
V
DD
15
GND 16
DIFF
OUT
/S6 17
A2
OUT
/S5 18
A1
OUT
/S4 19
A0
OUT
/S3 20
D11/S2 21
D10/S1 22
D9/S0 23
D8 24
FW PACKAGE
48-LEAD PLASTIC TSSOP
T
JMAX
= 150°C,
θ
JA
= 110°C/W
18501f
LTC1850/LTC1851
CO VERTER CHARACTERISTICS
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error (Bipolar and Unipolar)
Gain = 1 (PGA = 1)
Gain = 1 (PGA = 1)
Gain = 2 (PGA = 0)
Offset Error Match
Unipolar Gain Error
Gain = 1 (PGA = 1)
Gain = 2 (PGA = 0)
Unipolar Gain Error Match
Bipolar Gain Error
Gain = 1 (PGA = 1)
Gain = 2 (PGA = 0)
Bipolar Gain Error Match
Full-Scale Error Temperature Coefficient
(Note 8)
REFCOMP
≥
2V
REFCOMP
≥
2V
(Note 7)
CONDITIONS
The
q
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Notes 5, 6)
LTC1850
LTC1851
MIN
TYP
MAX MIN
TYP
MAX
q
q
q
A ALOG I PUT
The
q
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
SYMBOL
V
IN
PARAMETER
Analog Input Range (Note 9)
Unipolar, Gain = 1 (PGA = 1)
Unipolar, Gain = 2 (PGA = 0)
Bipolar, Gain = 1 (PGA = 1)
Bipolar, Gain = 2 (PGA = 0)
Analog Input Leakage Current
Analog Input Capacitance
CONDITIONS
4.75V
≤
V
DD
≤
5.25V
0 – REFCOMP
0 – REFCOMP/2
±REFCOMP/2
±REFCOMP/4
V
IN
> 0V < V
DD
, All Channels
Between Conversions (Gain = 1)
Between Conversions (Gain = 2)
During Conversions
q
q
q
I
IN
C
IN
t
ACQ
t
S(MUX)
t
AP
t
jitter
CMRR
Sample-and-Hold Acquisition Time
Multiplexer Settling Time (Includes t
ACQ
)
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Analog Input Common Mode Rejection Ratio
0V < (A
IN –
= A
IN +
) < 5V
U
U
UNITS
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm/°C
10
±0.25
±0.25
±
0.5
±0.5
±2
±2
±4
±0.5
12
±0.35
±0.25
±1
±1
±5
±7
±10
±1
±6
±10
±1
±6
±10
±1
15
q
q
±0.5
±1
±1
±2
With External 4.096V Reference
Applied to REFCOMP (Note 12)
±2
±4
±0.5
With External 4.096V Reference
Applied to REFCOMP (Note 12)
±2
±4
±0.5
15
U
MIN
TYP
MAX
UNITS
V
V
V
V
±1
15
25
5
50
50
– 0.5
2
60
150
150
µA
pF
pF
pF
ns
ns
ns
ps
RMS
dB
18501f
3
LTC1850/LTC1851
DY A IC ACCURACY
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
Unipolar, PGA = 0
Unipolar, PGA = 1
Bipolar, PGA = 0
Bipolar, PGA = 1
Signal-to-(Noise + Distortion) Ratio
Unipolar, PGA = 0
Unipolar, PGA = 1
Bipolar, PGA = 0
Bipolar, PGA = 1
Total Harmonic Distortion
Unipolar, PGA = 0
Unipolar, PGA = 1
Bipolar, PGA = 0
Bipolar, PGA = 1
Spurious-Free Dynamic Range
Unipolar, PGA = 0
Unipolar, PGA = 1
Bipolar, PGA = 0
Bipolar, PGA = 1
S/(N+D)
THD
SFDR
I TER AL REFERE CE
PARAMETER
REFOUT Output Voltage
REFOUT Output Temperature Coefficient
REFOUT Line Regulation
Reference Buffer Gain
REFCOMP Output Voltage
REFCOMP Impedance
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
I
OZ
C
OZ
I
SOURCE
I
SINK
PARAMETER
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
The
q
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
V
DD
= 5.25V
V
DD
= 4.75V
V
IN
= 0V to V
DD
V
DD
= 4.75V, I
O
= –10µA
V
DD
= 4.75V, I
O
= – 200µA
V
DD
= 4.75V, I
O
= 160µA
V
DD
= 4.75V, I
O
= 1.6mA
CS High (Note 9)
V
OUT
= 0V
V
OUT
= V
DD
q
q
q
Hi-Z Output Leakage D11 to D0, AD
OUT
, A1
OUT
, A2
OUT
, DIFF
OUT
V
OUT
= 0V to V
DD
, CS High
Hi-Z Capacitance D11 to D0, AD
OUT
, A1
OUT
, A2
OUT
, DIFF
OUT
Output Source Current
Output Sink Current
4
U
U
U
W U
(Note 5)
CONDITIONS
47kHz Input Signal
61.6
61.7
61.6
61.7
47kHz Input Signal
61.0
61.0
61.0
61.2
47kHz Input Signal,
First 5 Harmonics
–76
–78
–81
–80
74
80
84
82
70
71
71
72
–80
–82
–87
–86
82
86
90
88
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
71
72
71
72
dB
dB
dB
dB
LTC1850
MIN
TYP
MAX
LTC1851
MIN
TYP
MAX
UNITS
47kHz Input Signal
U
U
T
A
= 25°C. (Notes 5, 6)
CONDITIONS
I
OUT
= 0
I
OUT
= 0
V
REFCOMP
/V
REFIN
External 2.5V Reference
Internal 2.5V Reference
REFIN = V
DD
1.636
4.090
4.060
MIN
2.48
TYP
2.50
±15
0.01
1.638
4.096
4.096
6.4
1.640
4.100
4.132
MAX
2.52
UNITS
V
ppm/°C
LSB/V
V/V
V
V
kΩ
MIN
2.4
TYP
MAX
0.8
±5
UNITS
V
V
µA
pF
V
V
2
4.5
q
q
q
q
4.0
0.05
0.10
0.4
±10
15
– 20
30
V
V
µA
pF
mA
mA
18501f
LTC1850/LTC1851
POWER REQUIRE E TS
SYMBOL
V
DD
OV
DD
I
DD
P
DISS
PARAMETER
Positive Supply Voltage
Output Positive Supply Voltage
Positive Supply Current
Power Dissipation
Power Down Positive Supply Current
Nap Mode
Sleep Mode
Power Down Power Dissipation
Nap Mode
Sleep Mode
The
q
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
(Note 10)
(Note 10)
V
DD
= V
DD
= OV
DD
= 5V,
f
SAMPLE
= 1.25MHz
q
q
q
q
TI I G CHARACTERISTICS
SYMBOL
f
SAMPLE(MAX)
t
CONV
t
ACQ
t
1
t
2
t
3
t
4
PARAMETER
Maximum Sampling Frequency
Acquisition + Conversion
Conversion Time
Acquisition Time
CS to RD Setup Time
CS to CONVST Setup Time
CS to SHDN Setup Time
SHDN to CONVST Wake-Up Time
The
q
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
q
q
q
q
t
5
t
6
t
7
t
8
t
9
t
10
CONVST Low Time
CONVST to BUSY Delay
Data Ready Before BUSY
Delay Between Conversions
Wait Time RD After BUSY
Data Access Time After RD
t
11
BUS Relinquish Time
0°C to 70°C
– 40°C to 85°C
q
q
q
t
12
t
13
t
14
t
15
t
16
RD Low Time
CONVST High Time
Latch Setup Time
Latch Hold Time
WR Low Time
(Note 10)
(Notes 9, 10)
(Notes 9, 10)
(Note 10)
U W
MIN
4.75
2.7
TYP
MAX
5.25
5.25
UNITS
V
V
mA
mW
mA
µA
mW
mW
8
40
1
50
5
0.25
10
50
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
SHDN = 0V, CS = 0V
SHDN = 0V, CS = 5V
UW
MIN
1.25
TYP
MAX
800
650
150
UNITS
MHz
ns
ns
ns
ns
ns
(Notes 9, 10)
(Notes 9, 10)
(Notes 9, 10)
Nap Mode (Note 10)
Sleep Mode, 10µF REFCOMP
Bypass Capacitor (Note 10)
(Notes 10, 11)
C
L
= 25pF
q
q
0
10
200
200
10
ns
ns
ms
ns
q
q
q
50
10
60
20
15
50
–5
20
35
45
45
60
30
35
40
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
18501f
(Note 10)
C
L
= 25pF
q
q
q
C
L
= 100pF
q
25
10
t
10
50
10
10
50
q
q
q
q
5
FPGA/CPLD
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