DSC12X2/3/4
High Performance Differential MEMS Oscillators
Features
• Very Low RMS Phase Jitter: <650 fs (typ.)
• High Stability: ±20 ppm, ±25 ppm, ±50 ppm
• Wide Temperature Range:
- Automotive: –40°C to +125°C (DSC12x
LVDS Only)
- Ext. Industrial: –40°C to +105°C
- Industrial: –40°C to +85°C
- Commercial: –20°C to +70°C
• Supports LVPECL, LVDS, or HCSL Differential
Outputs
• PCIe Gen1-5 Compliant Output
• Wide Frequency Range: 2.5 MHz to 450 MHz
• Small Industry Standard Footprints:
- 2.5 mm x 2.0 mm
- 3.2 mm x 2.5 mm
- 5.0 mm x 3.2 mm
- 7.0 mm x 5.0 mm
• Excellent Shock and Vibration Immunity
- Qualified to MIL-STD-883
• High Reliability
- 20x Better MTF than Quartz Oscillators
• Supply Range of 2.25 to 3.6V
• Standby, Frequency Select, and Output Enable
Functions
• Lead-Free and RoHS Compliant
General Description
The DSC12x2/3/4 family of high performance
oscillators utilizes the latest generation of silicon
MEMS technology that reduces close-in noise and
provides excellent jitter and stability over a wide range
of supply voltages and temperatures. By eliminating
the need for quartz or SAW technology, MEMS
oscillators significantly enhance reliability and
accelerate product development, while meeting
stringent clock performance criteria for a variety of
communications, storage, and networking applications.
The DSC12x2/3/4 family features a control function on
pin 1 or pin 2 that permits either a standby feature
(complete power down when STDBY is low), output
enable (output is tri-stated with OE low), or a frequency
select (choice of two frequencies selected by FS
high/low). See the Product Identification System
section for detailed information.
All oscillators are available in industry-standard
packages, including the small 2.5 mm x 2.0 mm, and
are “drop-in” replacements for standard 6-pin
LVPECL/LVDS/HCSL crystal oscillators.
Package Types
DSC12x2/3/4
6-Lead CDFN/VDFN
OE/STDBY/FS
NC
GND
1
2
6
5
VDD
CLK–
CLK+
Applications
•
•
•
•
•
•
Storage Area Networks
Passive Optical Networks
10/100G Ethernet
HD/SD/SDI Video and Surveillance
PCI Express Gen 1/2/3/4
Display Port
3
4
NC
OE/STDBY/FS
GND
1
2
6
5
VDD
CLK–
CLK+
3
4
2019-2021 Microchip Technology Inc.
DS20006011C-page 1
DSC12X2/3/4
Functional Block Diagrams
Pin 1
OE/STDBY/FS
DIGITAL
CONTROL
SUPPLY
REGULATION
Pin 6
VDD
Pin 2
NC
MEMS
RESONATOR
TEMP SENSOR +
CONTROL &
COMPENSATION
PLL
OUTPUT
DIV
Pin 5
CLK–
Pin 4
CLK+
Pin 3
GND
Pin 1
NC
DIGITAL
CONTROL
SUPPLY
REGULATION
Pin 6
VDD
Pin 2
OE/STDBY/FS
MEMS
RESONATOR
TEMP SENSOR +
CONTROL &
COMPENSATION
PLL
OUTPUT
DIV
Pin 5
CLK–
Pin 4
CLK+
Pin 3
GND
DS20006011C-page 2
2019-2021 Microchip Technology Inc.
DSC12X2/3/4
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Supply Voltage .......................................................................................................................................... –0.3V to +4.0V
Input Voltage .....................................................................................................................................–0.3V to V
DD
+ 0.3V
ESD Protection (HBM) ............................................................................................................................................... 4 kV
ESD Protection (MM) ................................................................................................................................................400V
ESD Protection (CDM) ............................................................................................................................................ 1.5 kV
† Notice:
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the device at those or any other conditions above those indicated
in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Characteristics:
V
DD
= 2.5V ±10% or 3.3V ±10%; T
A
= –40°C to +105°C, unless noted.
Parameters
Supply Voltage
Sym.
V
DD
Min.
2.25
—
—
Supply Current
I
DD
—
—
Standby Current
I
STDBY_
—
—
Frequency Stability
Δf
—
—
Aging
Startup Time
Input Logic Levels
Output Disable Time
Output Enable Time
Enable Pull-Up Resistor
Note 1:
2:
3:
4:
5:
6:
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
—
—
—
—
0.75 x V
DD
—
—
—
—
—
Typ.
—
50
32
40
23
2.5
—
—
—
—
—
5.5
—
—
—
—
—
1.5
Max.
3.63
—
—
—
—
5
±20
±25
±50
±5
±1
6
—
0.25 x V
DD
25
6
350
—
ppm
ms
V
ns
ms
ns
MΩ
ppm
µA
mA
Units
V
Note 1
LVPECL, f
OUT
= 100 MHz
LVDS, f
OUT
= 100 MHz
HCSL, f
OUT
= 100 MHz
Output disabled (tri-state),
f
OUT
= 100 MHz
Input pin = STDBY = Asserted,
(V
DD
= 3.3V)
Includes frequency variations
due to initial tolerance, temp.,
and power supply voltage
First year @ 25°C
Per year after first year
From 90% V
DD
to valid clock
output, T = +25°C,
Note 2
Input logic high
Input logic low
Note 3
STDBY
OE
Pull-up resistor on pin 1,
Note 4
Conditions
V
DD
pin should be filtered with 0.1 µF capacitor.
t
SU
is time to 100 ppm stable output frequency after V
DD
is applied and outputs are enabled.
t
DA
: See the Output Waveforms and the Test Circuits sections for more information.
Output is enabled if pad is floated (not connected).
Jitter limits are established by Gen 1.1, Gen 2.1, Gen 3.0, Gen4.0, and Gen 5.0 PCIe standards.
Guaranteed by design, but not tested.
2019-2021 Microchip Technology Inc.
DS20006011C-page 3
DSC12X2/3/4
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics:
V
DD
= 2.5V ±10% or 3.3V ±10%; T
A
= –40°C to +105°C, unless noted.
Parameters
LVPECL (DSC12x2)
Frequency
f
0
V
OH
Output Logic Levels
V
OL
Peak-to-Peak Output Swing
Output Transition Time
Output Duty Cycle
Period Jitter RMS
Period Jitter Peak-to-Peak
Integrated Phase Noise
(Random)
LVDS (DSC12x3)
Frequency
Output Offset Voltage
Peak-to-Peak Output Swing
Output Transition Time
Output Duty Cycle
Period Jitter RMS
Period Jitter Peak-to-Peak
Period Jitter RMS
Period Jitter Peak-to-Peak
f
0
V
OS
V
PP
t
R
t
F
SYM
J
PER
J
PTP
J
PER
J
PTP
2.3
1.15
250
120
40
—
—
—
—
—
Integrated Phase Noise
(Random)
J
PH
—
Note 1:
2:
3:
4:
5:
6:
0.9
—
—
1.25
350
170
—
2.5
20
3
25
0.65
450
1.35
150
220
52
—
—
—
—
—
ps
RMS
MHz
V
mV
ps
%
ps
ps
ps
ps
—
R = 100Ω Differential
Single-Ended
20% to 80%, R
L
= 100Ω
Differential
f
0
= 156.25 MHz, 10k cycles
f
0
= 156.25 MHz, 10k cycles
f
0
= 156.25 MHz,
T
A
= –40°C to +125°C
f
0
= 156.25 MHz,
T
A
= –40°C to +125°C
12 kHz to 20 MHz
@156.25 MHz,
T
A
= –40°C to +105°C
2 kHz to 20 MHz
@156.25 MHz,
T
A
= –40°C to +105°C
V
PP
t
R
t
F
SYM
J
PER
J
PTP
J
PH
2.5
V
DD
–
1.145
—
—
—
—
48
—
—
—
—
—
—
800
200
250
—
2.0
20
0.65
450
—
V
DD
–
1.695
—
250
300
52
—
—
—
V
R
L
= 50Ω
MHz
—
Sym.
Min.
Typ.
Max.
Units
Conditions
mV
ps
%
ps
ps
ps
RMS
Single-Ended
20% to 80%, R
L
= 50Ω
Differential
f
0
= 156.25 MHz, 10k cycles
f
0
= 156.25 MHz, 10k cycles
12 kHz to 20 MHz
@156.25 MHz
V
DD
pin should be filtered with 0.1 µF capacitor.
t
SU
is time to 100 ppm stable output frequency after V
DD
is applied and outputs are enabled.
t
DA
: See the Output Waveforms and the Test Circuits sections for more information.
Output is enabled if pad is floated (not connected).
Jitter limits are established by Gen 1.1, Gen 2.1, Gen 3.0, Gen4.0, and Gen 5.0 PCIe standards.
Guaranteed by design, but not tested.
DS20006011C-page 4
2019-2021 Microchip Technology Inc.
DSC12X2/3/4
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Characteristics:
V
DD
= 2.5V ±10% or 3.3V ±10%; T
A
= –40°C to +105°C, unless noted.
Parameters
HCSL (DSC12x4)
Frequency
Output Logic Levels
Peak-to-Peak Output Swing
Output Transition Time
Output Duty Cycle
Period Jitter RMS
Period Jitter Peak-to-Peak
f
0
V
OH
V
OL
V
PP
t
R
t
F
SYM
J
PER
J
PTP
2.3
0.64
—
—
200
250
48
—
—
—
Integrated Phase Noise
(Random)
J
PH
—
—
T
J
J
RMS-CCHF
Sym.
Min.
Typ.
Max.
Units
Conditions
—
—
—
750
260
370
—
2
16
0.617
0.460
0.212
3.42
0.247
0.08
0.107
0.107
0.043
450
—
0.1
—
400
500
52
—
—
—
—
—
86
3.1
3.0
1.0
0.30
0.12
MHz
V
mV
ps
%
ps
ps
—
R
L
= 50Ω
Single-Ended
20% to 80%, R
L
= 50Ω
Differential
f
0
= 100.00 MHz, 10k cycles
f
0
= 100.00 MHz, 10k cycles
12 kHz to 20 MHz @100 MHz
T
A
= –40°C to +105°C
100 kHz to 20 MHz @100 MHz
ps
RMS
T
A
= –40°C to +105°C
1.875 MHz to 20 MHz
@100 MHz
T
A
= –40°C to +105°C
ps
PP
ps
RMS
ps
RMS
PCIe Gen 1.1, T
J
= D
J
+14.069
x R
J
(BER 10
–12
),
Note 5
PCIe Gen 2.1, 1.5 MHz to
Nyquist,
Note 5
PCIe Gen 2.1, 10 kHz to 1.5 MHz,
Note 5
PCIe Gen 3.0, Note 5
ps
RMS
PCIe Gen 4.0, 16 GHz,
Note 6
PCIe Gen 5.0, 32 GHz,
Note 6
—
—
—
—
Phase Jitter
J
RMS-CCHF
J
RMS-CC
Note 1:
2:
3:
4:
5:
6:
—
—
V
DD
pin should be filtered with 0.1 µF capacitor.
t
SU
is time to 100 ppm stable output frequency after V
DD
is applied and outputs are enabled.
t
DA
: See the Output Waveforms and the Test Circuits sections for more information.
Output is enabled if pad is floated (not connected).
Jitter limits are established by Gen 1.1, Gen 2.1, Gen 3.0, Gen4.0, and Gen 5.0 PCIe standards.
Guaranteed by design, but not tested.
2019-2021 Microchip Technology Inc.
DS20006011C-page 5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
