TM
HM-65262/883
16K x 1 Asynchronous
CMOS Static RAM
Description
The HM-65262/883 is a CMOS 16384 x 1-bit Static Ran-
dom Access Memory manufactured using the Intersil
Advanced SAJI V process. The device utilizes asynchro-
nous circuit design for fast cycle times and ease of use.
The HM-65262/883 is available in both JEDEC Standard
20 pin, 0.300 inch wide CERDIP and 20 pad CLCC pack-
ages, providing high board-level packing density. Gated
inputs lower standby current, and also eliminate the need
for pull-up or pull-down resistors.
The HM-65262/883, a full CMOS RAM, utilizes an array of
six transistor (6T) memory cells for the most stable and
lowest possible standby supply current over the full military
temperature range. In addition to this, the high stability of
the 6T RAM cell provides excellent protection against soft
errors due to noise and alpha particles. This stability also
improves the radiation tolerance of the RAM over that of
four transistor (4T) devices.
March 1997
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Fast Access Time . . . . . . . . . . . . . . . . . . . 70/85ns Max
• Low Standby Current. . . . . . . . . . . . . . . . . . . . 50
µ
A Max
• Low Operating Current . . . . . . . . . . . . . . . . . 50mA Max
• Data Retention at 2.0V . . . . . . . . . . . . . . . . . . . 20µA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout
• No Clocks or Strobes Required
• Temperature Range . . . . . . . . . . . . . . . +55
o
C to +125
o
C
• Gated Inputs-No Pull-Up or Pull-Down Resistors
Required
• Equal Cycle and Access Time
• Single 5V Supply
Ordering Information
70ns/20µA
-
HM4-65262B/883
85ns/20µA
HM1-65262/883
HM4-65262/883
85ns/400µA
-
-
TEMP. RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
PACKAGE
CERDIP
CLCC
PKG. NO.
F20.3
J20.C
Pinouts
HM1-65262/883 (CERDIP)
TOP VIEW
HM-65262 (CLCC)
TOP VIEW
VCC
A13
A1
A0
A0
A1
A2
A3
A4
A5
A6
Q
W
1
2
3
4
5
6
7
8
9
20 VCC
19 A13
18 A12
17 A11
16 A10
15 A9
14 A8
13 A7
12 D
11 E
A2 3
A3 4
A4 5
A5 6
A6 7
Q 8
2
1 20 19
18 A12
17 A11
16 A10
15 A9
14 A8
13 A7
A0 - A13
E
Q
D
VSS/GND
VCC
W
Address Input
Chip Enable/Power Down
Data Out
Data In
Ground
Power (+5)
Write Enable
9 10 11 12
GND
E
W
D
GND 10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
FN3003.2
204
HM-65262/883
Functional Diagram
A0
A1
A2
A3
A4
A12
A13
A
7
ROW
ROW
ADDRESS
DECODER 128 MEMORY ARRAY
BUFFER A (1 OF 128)
128 X 128
7
128
COLUMN DECODER
(1 OF 128)
AND I / O CIRCUITRY
A
7
A
7
Q
D
E
COLUMN
ADDRESS BUFFERS
W
205
A7
A8
A9
A10
A11
A5
A6
HM-65262/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input or Output Voltage Applied for all Grades . . . . . -0.3V to VCC +0.3V
Typical Derating Factor. . . . . . . . . . . . . . . .5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical)
θ
JA
θ
JC
o
C/W
CERDIP Package. . . . . . . . . . . . . . . . . .
66
13
o
C/W
o
C/W
CLCC Package . . . . . . . . . . . . . . . . . . .
75
18
o
C/W
o
C to +150
o
C
Maximum Storage Temperature Range . . . . . . . . . . . . -65
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175
o
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . +300
o
C
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26256 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . . -55
o
C to +125
o
C
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage (VIH)
. . . . . . . . . . . . . . . . . . . . . . . . . . ±2.2V
to VCC
Data Retention Supply Voltage . . . . . . . . . . . . . . . . . . . 2.0V to 4.5V
Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max.
TABLE 1. HM-65262/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
(NOTE 1)
CONDITIONS
VCC = 4.5V, IO = -4.0mA
VCC = 4.5V, IO = 8.0mA
VCC = 5.5V, E = 5.5V, VO = GND
or VCC
VCC = 5.5V, VI = GND or VCC
VCC = 5.5V, IO = 0mA, E = VCC
-0.3V
VCC = 5.5V, IO = 0mA, E = 2.2V
VCC = 5.5V, (Note 2), f = 1MHz, E
= 0.8V
VCC = 2.0V, IO = 0mA, E = VCC
-0.3V
VCC = 5.5V, IO = 0mA, E = 0.8V
VCC = 4.5V (Note 3)
GROUP A
SUB-GROUPS
1, 2, 3
1, 2, 3
1, 2, 3
DC PARAMETER
High Level Output Voltage
Low Level Output Voltage
High Impedance Output
Leakage Current
Input Leakage Current
Standby Supply Current
SYMBOL
VOH1
VOL
IOZ
TEMPERATURE
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
MIN
2.4
-
-1.0
MAX
-
0.4
1.0
UNITS
V
V
µA
µA
µA
II
ICCSB1
1, 2, 3
1, 2, 3
-1.0
-
1.0
50
Standby Supply Current
Operating Supply
Current
Data Retention Supply
Current
Enable Supply Current
Functional Test
ICCSB
ICCOP
1, 2, 3
1, 2, 3
-
-
5
50
mA
mA
µA
ICCDR
1, 2, 3
-
20
ICCEN
FT
1, 2, 3
7, 8A, 8B
-
-
50
-
mA
-
NOTES:
1. All voltages referenced to device GND.
2. Typical derating 1.5mA/MHz increase in ICCOP.
3. Tested as follows: f = 2MHz, VIH = 2.4V, VIL = 0.4V, IOH = -4.0mA, IOL = 4.0mA, VOH
≥
1.5V, and VOL
≤
1.5V.
TABLE 2. HM-65262/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
AC PARAMETER
Read/Write/Cycle
Time
Address Access
Time
SYMBOL
(1) TAVAX
(NOTES 1, 2)
CONDITIONS
VCC = 4.5V and 5.5V
GROUP A
SUB-
GROUPS
9, 10, 11
HM-
65262B/883
LIMITS
TEMPERATURE
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
HM-65262/883
LIMITS
MIN
85
MIN
70
MAX
-
MAX
-
UNITS
ns
(2) TAVQV
VCC = 4.5V and 5.5V
9, 10, 11
-
70
-
85
ns
206
HM-65262/883
TABLE 2. HM-65262/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
Device Guaranteed and 100% Tested
AC PARAMETER
Chip Enable to End
of Write
Chip Enable Access
Time
Address Hold Time
Address Setup Time
Address Valid to
End of Write
Address Setup Time
Address Hold Time
Address Valid to
End of Writes
Write Enable Pulse
Write
Data Setup Time
Data Hold Time
Enable Pulse Width
Write to End of
Write
Data Setup Time
Data Hold Time
SYMBOL
(3) TELWH
(NOTES 1, 2)
CONDITIONS
VCC = 4.5V and 5.5V
GROUP A
SUB-
GROUPS
9, 10, 11
HM-
65262B/883
LIMITS
TEMPERATURE
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
HM-65262/883
LIMITS
MIN
65
MIN
55
MAX
-
MAX
-
UNITS
ns
(4) TELQV
VCC = 4.5V and 5.5V
9, 10, 11
-
70
-
85
ns
(5) TWHAX
(6) TAVWL
(7) TAVWH
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
9, 10, 11
9, 10, 11
9, 10, 11
0
0
55
-
-
-
0
0
65
-
-
-
ns
ns
ns
(8) TAVEL
(9) TEHAX
(10) TAVEH
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
9, 10, 11
9, 10, 11
9, 10, 11
0
0
55
-
-
-
0
0
65
-
-
-
ns
ns
ns
(11) TWLWH
VCC = 4.5V and 5.5V
9, 10, 11
40
-
45
-
ns
(12) TDVWH
(13) TWHDX
(14) TELEH
(15) TWLEH
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
30
0
55
40
-
-
-
-
35
0
65
45
-
-
-
-
ns
ns
ns
ns
(16) TDVEH
(17) TEHDX
VCC = 4.5V and 5.5V
VCC = 4.5V and 5.5V
9, 10, 11
9, 10, 11
30
0
-
-
35
0
-
-
ns
ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC -2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1
TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
3. TAVQV = TELQV + TAVEL.
TABLE 3. HM-65262/883 ELECTRICAL PERFORMANCE SPECIFICATIONS, AC AND DC
LIMITS
PARAMETER
Input Capacitance
SYMBOL
(NOTE 1)
CONDITIONS
VCC = Open, f = 1MHz, All
Measurements Refer-
enced To Device Grounds
VCC = Open, f = 1MHz, All
Measurements Refer-
enced To Device Grounds
Output Capacitance
NOTES
1, 2
TEMPERATURE
T
A
= +25
o
C
MIN
-
MAX
10
UNITS
pF
CIN
1, 3
T
A
= +25
o
C
-
6
pF
CO
VCC = Open, f = 1MHz, All
Measurements Refer-
enced To Device Grounds
VCC = Open, f = 1MHz, All
Measurements Refer-
enced To Device Grounds
1, 2
T
A
= +25
o
C
-
12
pF
1, 3
T
A
= +25
o
C
-
8
pF
207
HM-65262/883
TABLE 3. HM-65262/883 ELECTRICAL PERFORMANCE SPECIFICATIONS, AC AND DC (Continued)
LIMITS
PARAMETER
Write Enable to Output in High Z
SYMBOL
(NOTE 1)
CONDITIONS
VCC = 4.5V and 5.5V
NOTES
1
TEMPERATURE
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C
-55
o
C
≤
T
A
≤
+125
o
C-
MIN
-
MAX
40
UNITS
ns
(18)
TWLQZ
(19)
TWHQX
(20)
TELQX
Write Enable High to Output ON
VCC = 4.5V and 5.5V
1
0
-
ns
Chip Enable to Output ON
VCC = 4.5V and 5.5V
1
5
-
ns
Output Enable High to Output in
High Z
Chip Disable to Output Hold Time
(21) TEHQZ
VCC = 4.5V and 5.5V
(22) TE-
HQX
VCC = 4.5V and 5.5V
1
-
40
ns
1
5
-
ns
Address Invalid Output Hold Time
High Level Output Voltage
(23) TAXQX
VCC = 4.5V and 5.5V
(24) VOH2
VCC = 4.5V, IO = -100mA
1
1
5
VCC -0.4V
-
-
ns
V
NOTES:
1. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics.
2. Applies to DIP device types only.
3. Applies to LCC device types only.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS
Initial Test
Interim Test
PDA
Final Test
Group A
Groups C & D
METHOD
100%/5004
100%/5004
100%/5004
100%/5004
Samples/5005
Samples/5005
SUBGROUPS
-
1, 7, 9
1
2, 3, 8A, 8B, 10, 11
1, 2, 3, 7, 8A, 8B, 9, 10, 11
1, 7, 9
208
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