Section I. Stratix GX
Device Family Data Sheet
This section provides the data sheet specifications for Stratix
®
GX
devices. It contains feature definitions of the internal architecture,
configuration information, testing information, DC operating conditions,
and AC timing parameters.
This section includes the following chapters:
■
■
■
■
■
■
■
Chapter 1, Introduction to the Stratix GX Device Data Sheet
Chapter 2, Stratix GX Transceivers
Chapter 3, Source-Synchronous Signaling With DPA
Chapter 4, Stratix GX Architecture
Chapter 5, Configuration & Testing
Chapter 6, DC & Switching Characteristics
Chapter 7, Reference & Ordering Information
Revision History
The table below shows the revision history for
Chapters 1
through
7.
Chapter(s)
1
2
3
4
5
6
7
Date / Version
February 2005, v1.0
February 2005, v1.0
August 2005, v1.1
February 2005, v1.0
February 2005, v1.0
August 2005, v1.1
February 2005, v1.0
Changes Made
Initial Release.
Initial Release.
Added Note (3) to Figure 3-7.
Initial Release.
Initial Release.
Updated Tables 6-7 and 6-50.
Initial Release.
Altera Corporation
Section I–1
Preliminary
Stratix GX Device Family Data Sheet
Stratix GX Device Handbook, Volume 1
Section I–2
Preliminary
Altera Corporation
1. Introduction to the
Stratix GX Device Data Sheet
SGX51001-1.0
Overview
The Stratix
®
GX family of devices is Altera’s second FPGA family to
combine high-speed serial transceivers with a scalable, high-performance
logic array. Stratix GX devices include 4 to 20 high-speed transceiver
channels, each incorporating clock data recovery (CDR) technology and
embedded SERDES capability at data rates of up to 3.1875 gigabits per
second (Gbps). These transceivers are grouped by four-channel
transceiver blocks, and are designed for low power consumption and
small die size. The Stratix GX FPGA technology is built upon the Stratix
architecture, and offers a 1.5-V logic array with unmatched performance,
flexibility, and time-to-market capabilities. This scalable,
high-performance architecture makes Stratix GX devices ideal for
high-speed backplane interface, chip-to-chip, and communications
protocol-bridging applications.
■
Features
Transceiver block features are as follows:
●
High-speed serial transceiver channels with CDR provides
500-megabits per second (Mbps) to 3.1875-Gbps full-duplex
operation
●
Devices are available with 4, 8, 16, or 20 high-speed serial
transceiver channels providing up to 127.5 Gbps of full-duplex
serial bandwidth
●
Support for transceiver-based protocols, including 10 Gigabit
Ethernet attachment unit interface (XAUI), Gigabit Ethernet
(GigE), and SONET/SDH
●
Compatible with PCI Express, SMPTE 292M, Fibre Channel, and
Serial RapidIO I/O standards
●
Programmable differential output voltage (V
OD
), pre-emphasis,
and equalization settings for improved signal integrity
●
Individual transmitter and receiver channel power-down
capability implemented automatically by the Quartus
®
II
software for reduced power consumption during non-operation
●
Programmable transceiver-to-FPGA interface with support for
8-, 10-, 16-, and 20-bit wide data paths
●
1.5-V pseudo current mode logic (PCML) for 500 Mbps to
3.1875 Gbps
●
Support for LVDS, LVPECL, and 3.3-V PCML on reference
clocks and receiver input pins (AC-coupled)
●
Built-in self test (BIST)
●
Hot insertion/removal protection circuitry
Altera Corporation
February 2005
1–1
Features
●
●
●
●
●
Pattern detector and word aligner supports programmable
patterns
8B/10B encoder/decoder performs 8- to 10-bit encoding and 10-
to 8-bit decoding
Rate matcher compliant with IEEE 802.3-2002 for GigE mode
and with IEEE 802-3ae for XAUI mode
Channel bonding compliant with IEEE 802.3ae (for XAUI mode
only)
Device can bypass some transceiver block features if necessary
■
FPGA features are as follows:
●
10,570 to 41,250 logic elements (LEs); see
Table 1–1
●
Up to 3,423,744 RAM bits (427,968 bytes) available without
reducing logic resources
●
TriMatrix
™
memory consisting of three RAM block sizes to
implement true dual-port memory and first-in-out (FIFO)
buffers
●
Up to 16 global clock networks with up to 22 regional clock
networks per device region
●
High-speed DSP blocks provide dedicated implementation of
multipliers (faster than 300 MHz), multiply-accumulate
functions, and finite impulse response (FIR) filters
●
Up to eight general usage phase-locked loops (four enhanced
PLLs and four fast PLLs) per device provide spread spectrum,
programmable bandwidth, clock switchover, real-time PLL
reconfiguration, and advanced multiplication and phase
shifting
●
Support for numerous single-ended and differential I/O
standards
●
High-speed source-synchronous differential I/O support on up
to 45 channels for 1-Gbps performance
●
Support for source-synchronous bus standards, including
10-Gigabit Ethernet XSBI, Parallel RapidIO, UTOPIA IV,
Network Packet Streaming Interface (NPSI), HyperTransport
TM
technology, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4
●
Support for high-speed external memory, including zero bus
turnaround (ZBT) SRAM, quad data rate (QDR and QDRII)
SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM
(FCRAM), and single data rate (SDR) SDRAM
●
Support for multiple intellectual property megafunctions from
Altera
®
MegaCore
®
functions and Altera Megafunction Partners
Program (AMPP
SM
) megafunctions
●
Support for remote configuration updates
●
Dynamic phase alignment on LVDS receiver channels
1–2
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005
Introduction to the Stratix GX Device Data Sheet
Table 1–1. Stratix GX Device Features
Feature
LEs
Transceiver channels
Source-synchronous channels
M512 RAM blocks (32
×
18 bits)
M4K RAM blocks (128
×
36 bits)
M-RAM blocks (4K
×
144 bits)
Total RAM bits
Digital signal processing (DSP) blocks
Embedded multipliers
(1)
PLLs
Note to
Table 1–1:
(1)
This parameter lists the total number of 9- × 9-bit multipliers for each device. For the total number of 18- × 18-bit
multipliers per device, divide the total number of 9- × 9-bit multipliers by 2. For the total number of 36- × 36-bit
multipliers per device, decide the total number of 9- × 9-bit multipliers by 8.
EP1SGX10C
EP1SGX10D
10,570
4, 8
22
94
60
1
920,448
6
48
4
EP1SGX25C
EP1SGX25D
EP1SGX25F
25,660
4, 8, 16
39
224
138
2
1,944,576
10
80
4
EP1SGX40D
EP1SGX40G
41,250
8, 20
45
384
183
4
3,423,744
14
112
8
Stratix GX devices are available in space-saving FineLine BGA
®
packages
(refer to
Tables 1–2
and
1–3),
and in multiple speed grades (refer to
Table 1–4).
Stratix GX devices support vertical migration within the same
package (that is, you can migrate between the EP1SGX10C and
EP1SGX25C devices in the 672-pin FineLine BGA package). See the
Stratix GX device pin tables for more information. Vertical migration
means that you can migrate to devices whose dedicated pins,
configuration pins, and power pins are the same for a given package
across device densities. For I/O pin migration across densities, you must
cross-reference the available I/O pins using the device pin-outs for all
planned densities of a given package type, to identify which I/O pins it
is possible to migrate. The Quartus II software can automatically cross
reference and place all pins for migration when given a device migration
list.
Table 1–2. Stratix GX Package Options & I/O Pin Counts (Part 1
of 2)
Note (1)
Device
EP1SGX10C
EP1SGX10D
EP1SGX25C
672-Pin FineLine BGA
362
362
455
1,020-Pin FineLine BGA
Altera Corporation
February 2005
1–3
Stratix GX Device Handbook, Volume 1
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