FEATURES
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LTC1406
Low Power, 8-Bit, 20Msps,
Sampling A/D Converter
DESCRIPTION
The LTC
®
1406 is a 20Msps, 8-bit, sampling A/D converter
which draws only 150mW from a single 5V supply. This
easy-to-use device includes a high dynamic range sample-
and-hold with a 250MHz bandwidth.
The LTC1406’s full-scale input range is
±1V.
The inputs
can be driven differentially or one input can be tied to a
fixed voltage and the other input driven with a
±1V
bipolar
input. Maximum DC specifications include
±1LSB
DNL
and INL over temperature. Outstanding AC performance
includes 48.5dB S/(N + D) and 62dB THD with a 1MHz
input; 47.5dB S/(N + D) and 59dB THD at the Nyquist input
frequency of 10MHz.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 250MHz
bandwidth. The 60dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source.
The ADC has an 8-bit parallel output port with separate
power supply and ground allowing easy interface to 3V
digital systems. The pipelined architecture has five clock
cycles of data latency.
, LTC and LT are registered trademarks of Linear Technology Corporation.
Low Power, 8-Bit, 20Msps ADC
250MHz Internal Sample-and-Hold
7 Effective Bits at 70MHz Input Frequency
±1LSB
DNL and INL Max
Single 5V Supply and 150mW Dissipation
Power Down to 1µA
True Differential Inputs Reject Common Mode Noise
Accepts Single-Ended or Differential Input Signals
±1V
Differential or 2V Single-Ended Input Span
Analog Inputs Common Mode to V
DD
and GND
24-Pin Narrow SSOP Package
APPLICATIONS
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Telecommunications
Wireless Communications
Digital Cellular Telephones
CCDs and Image Scanners
Video Digitizing and Digital Television
Digital Color Copiers
High Speed Undersampling
Personal Computer Video
High Speed Data Acquisition
TYPICAL APPLICATION
Low Power, 20MHz, 8-Bit Sampling ADC
DV
DD
12
CLK
24
CLOCK
CIRCUITRY
23
22
21
A
IN+
A
IN–
7
TRACK-AND-
HOLD AMP
8-BIT
PIPELINE
ADC
DIGITAL
DATA
OUTPUT
DRIVERS
20
19
18
17
2.2V
2.5k
9
AV
DD
4
V
BIAS
1.95k
10
AGND
3
SHDN
5
V
REF
6
AGND
1
OGND
1406 BD
DGND
11
OV
DD
2
Effective Bits and Signal-to-Noise + Distortion
vs Input Frequency
8
7
OF/UF
6
EFFECTIVE BITS
D7
D6
D5
D4
D3
D2
D1
D0
5
4
3
2
1
0
100k
1M
10M
INPUT FREQUENCY (Hz)
8
16
15
U
U
U
50
44
38
S/(N + D) (dB)
32
100M
1406 TA02
1
LTC1406
ABSOLUTE
MAXIMUM
RATINGS
AV
DD
= OV
DD
= DV
DD
= V
DD
(Notes 1, 2)
PACKAGE/ORDER INFORMATION
TOP VIEW
OGND
OV
DD
SHDN
V
BIAS
V
REF
AGND
A
IN+
A
IN–
AV
DD
1
2
3
4
5
6
7
8
9
24 CLK
23 OF/UF
22 D7
21 D6
20 D5
19 D4
18 D3
17 D2
16 D1
15 D0
14 NC
13 NC
Supply Voltage (V
DD
) ................................................. 6V
Analog Input Voltage (Note 3) .... – 0.3V to (V
DD
+ 0.3V)
Digital Input Voltage (Note 4) .................. – 0.3V to 10V
Digital Output Voltage ................. – 0.3V to (V
DD
+ 0.3V)
Power Dissipation.............................................. 500mW
Ambient Operation Temperature Range
LTC1406C................................................ 0°C to 70°C
LTC1406I............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ORDER PART
NUMBER
LTC1406CGN
LTC1406IGN
AGND 10
DGND 11
DV
DD
12
GN PACKAGE
24-LEAD PLASTIC SSOP
T
JMAX
= 110°C,
θ
JA
= 85°C/ W
Consult factory for Military grade parts.
CO VERTER CHARACTERISTICS
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25°C.
(Notes 5, 6)
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
(Note 8)
With External 2.5V Reference
(Note 7)
CONDITIONS
q
q
q
q
MIN
8
TYP
±0.5
±0.25
±1
±1
MAX
±1
±1
±8
±5
UNITS
Bits
LSB
LSB
LSB
LSB
A ALOG I PUT
SYMBOL PARAMETER
V
IN
I
IN
C
IN
(Note 5)
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25°C.
CONDITIONS
4.75V
≤
V
DD
≤
5.25V
Voltage On Either A
IN+
or A
IN–
CLK = 0
CLK = 1
CLK = 0
q
q
q
MIN
0
TYP
±1
MAX
V
DD
±5
UNITS
V
V
µA
pF
pF
MHz
ns
ps
RMS
dB
V
Analog Input Span [(A
IN+
) – (A
IN–
)] (Note 9)
Input (A
IN+
or A
IN–
) Range
Analog Input Leakage Current
Analog Input Capacitance
Input Bandwidth
4
2
250
3
5
t
AP
t
jitter
CMRR
V
BIAS
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Analog Input Common Mode Rejection Ratio
Internal Bias Voltage
– 2.5V < (A
IN–
= A
IN+
) < 2.5V
No Load
60
2.2
2
U
W
U
U
W W
W
U
U
U
LTC1406
DY A IC ACCURACY
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25°C. (Note 5)
SYMBOL PARAMETER
S/(N + D) Signal-to-Noise Plus Distortion Ratio
THD
SFDR
IMD
Total Harmonic Distortion
Spurious Free Dynamic Range
Intermodulation Distortion
CONDITIONS
1MHz Input Signal
10MHz Input Signal
1MHz Input Signal, First 5 Harmonics
10MHz Input Signal, First 5 Harmonics
1MHz Input Signal
10MHz Input Signal
f
IN1
= 3.500977MHz, f
IN2
= 3.598633MHz
MIN
TYP
48.5
47.5
– 62
– 59
63
60
60
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
(Note 5)
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25°C.
SYMBOL PARAMETER
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
I
SOURCE
I
SINK
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Output Source Current
Output Sink Current
V
DD
= 4.75V, I
O
= – 10µA
V
DD
= 4.75V, I
O
= – 200µA
V
DD
= 4.75V, I
O
= 160µA
V
DD
= 4.75V, I
O
= 1.6mA
V
OUT
= 0V
V
OUT
= V
DD
q
q
DIGITAL I PUTS AND OUTPUTS
POWER REQUIRE E TS
SYMBOL PARAMETER
AV
DD
DV
DD
OV
DD
V
BIAS
V
REF
OGND
I
DD
P
D
Analog Positive Supply Voltage
Digital Positive Supply Voltage
Output Positive Supply Voltage
Internal Bias Voltage
Reference Voltage
Output Ground
Positive Supply Current
Power Dissipation
Power Down Positive Supply Current
Power Down Power Dissipation
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25°C.
CONDITIONS
(Note 10)
(Note 10)
(Note 10)
When Externally Driven (Note 10)
(Note 10)
(Note 10)
AV
DD
= DV
DD
= OV
DD
= 5V, f
SMPL
= 20MHz (Note 13)
SHDN = 0V, CLK = V
DD
or 0
SHDN = 0V, CLK = V
DD
or 0
q
q
UW
U
U
W U
CONDITIONS
V
DD
= 5.25V
V
DD
= 4.75V
V
IN
= 0V to V
DD
q
q
q
MIN
2.4
TYP
MAX
0.8
±5
UNITS
V
V
µA
pF
V
V
5
4.5
4.0
0.05
0.10
– 20
30
0.4
V
V
mA
mA
(Note 5)
MIN
4.75
4.75
2.7
1.9
2
0
30
150
1
5
2.2
2.5
TYP
MAX
5.25
5.25
5.25
2.5
3
2
45
225
10
50
UNITS
V
V
V
V
V
V
mA
mW
µA
µW
3
LTC1406
TI I G CHARACTERISTICS
The
q
denotes specifications which apply over the full operating temperature range, otherwise specifications are T
A
= 25°C. (Note 5)
SYMBOL
f
SMPL(MAX)
t
1
t
2
t
3
t
4
t
5
t
6
PARAMETER
Maximum Sampling Frequency
Clock Period
Pulse Width High
Pulse Width Low
Output Delay
Pipeline Delay
Aperture Delay
Aperture Jitter
Note 1:
Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2:
All voltage values are with respect to ground with DGND, OGND
and AGND wired together (unless otherwise noted).
Note 3:
When these pin voltages are taken below ground or above V
DD
,
they will be clamped by internal diodes. This product can handle input
currents greater than 100mA below ground or above V
DD
without latchup.
Note 4:
When these pin voltages are taken below ground they will be
clamped by internal diodes. This product can handle input currents up to
100mA below ground without latchup. These pins are not clamped to V
DD
.
Note 5:
V
DD
= 5V, f
SMPL
= 20MHz and t
r
= t
f
= 2ns unless otherwise
specified.
Note 6:
Linearity, offset and full-scale specifications apply for a single-
ended A
IN+
input with A
IN–
tied to V
REF
= 2.5V.
(Notes 11, 12)
(Notes 11, 12)
(Notes 11, 12)
C
L
= 15pF
CONDITIONS
q
q
q
q
TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency
52
48
44
40
36
32
28
24
20
16
12
8
4
0
100k
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
SIGNAL-TO-NOISE RATIO (dB)
S/(N + D) (dB)
1M
10M
INPUT FREQUENCY (Hz)
4
U W
UW
MIN
20
50
25
25
TYP
MAX
UNITS
MHz
ns
ns
ns
15
5
3
5
25
ns
Cycles
ns
ps
RMS
Note 7:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8:
Bipolar offset is the offset voltage measured from – 0.5LSB
when the output code flickers between 0111 1111 and 1000 0000.
Note 9:
Guaranteed by design, not subject to test.
Note 10:
Recommended operating conditions.
Note 11:
The falling CLK edge starts a conversion.
Note 12:
At the maximum conversion rate, deviation from a 50% duty
cycle results in interstage settling times < 25ns and performance may
be affected.
Note 13:
V
IN
= – Full Scale.
Signal-to-Noise Ratio vs
Input Frequency
52
48
44
40
36
32
28
24
20
16
12
8
4
0
100k
Distortion vs Input Frequency
0
–10
–20
–30
–40
–50
–60
–70
2ND HARMONIC
–80
100k
1M
10M
INPUT FREQUENCY (Hz)
100M
1406 G03
THD
3RD HARMONIC
100M
1406 G01
1M
10M
INPUT FREQUENCY (Hz)
100M
1406 G02
LTC1406
TYPICAL PERFORMANCE CHARACTERISTICS
Spurious-Free Dynamic Range
vs Input Frequency
70
SPURIOUS-FREE DYNAMIC RANGE (dB)
60
50
AMPLITUDE (dB)
40
30
20
10
0
100k
–30
–40
–50
–60
–70
–80
–90
DNL EOC ERROR (LSB)
1M
10M
INPUT FREQUENCY (Hz)
Integral Nonlinearity
vs Output Code
1.0
COMMON MODE REJECTION (dB)
INL EOC ERROR (LSB)
0.5
50
40
30
20
10
0
100k
SUPPLY CURRENT (mA)
0
–0.5
–1.0
0
32
64
96 128 160 192 224 256
OUTPUT CODE
1406 G07
PIN FUNCTIONS
OGND (Pin 1):
Digital Data Output Ground. Tie to analog
ground plane. May be tied to logic ground if desired.
OV
DD
(Pin 2):
Digital Data Output Supply. Normally tied to
5V, can be used to interface with 3V digital logic. Bypass
to OGND with 10µF tantalum in parallel with 0.1µF or 10µF
ceramic.
SHDN (Pin 3):
Power Shutdown Input. Logic low selects
shutdown.
V
BIAS
(Pin 4):
Internal Bias Voltage. Internally set to 2.2V.
Bypass to analog ground plane with 10µF tantalum in par-
allel with 0.1µF or 10µF ceramic.
V
REF
(Pin 5):
External 2.5V Reference Input. Bypass to
analog ground plane with 10µF tantalum in parallel with
0.1µF or 10µF ceramic.
AGND (Pin 6):
Analog Ground. Tie to analog ground plane.
A
IN+
(Pin 7):
±1V
Input. The maximum output code
occurs when [(A
IN+
) – (A
IN–
)] = 1V. The minimum output
code occurs when [(A
IN+
) – (A
IN–
)] = – 1V.
A
IN–
(Pin 8):
±1V
Input. The maximum output code
occurs when [(A
IN+
) – (A
IN–
)] = 1V. The minimum output
code occurs when [(A
IN+
) – (A
IN–
)] = – 1V. For single-
ended operation, tie A
IN–
to a DC voltage (e.g., V
REF
).
U W
1406 G04
Intermodulation Distortion Plot
0
–10
–20
f
SAMPLE
= 20MHz
f
IN1
= 3.500977MHz
f
IN2
= 3.598633MHz
0.5
1.0
Differential Nonlinearity
vs Output Code
0
–0.5
100M
–100
0
1
2
3 4 5 6 7
FREQUENCY (MHz)
8
9
10
–1.0
0
32
64
96 128 160 192 224 256
OUTPUT CODE
1406 G06
1406 G05
Input Common Mode Rejection
vs Input Frequency
70
60
Supply Current vs
Sampling Frequency
35
30
25
20
15
10
5
0
100k
1M
10M
INPUT FREQUENCY (Hz)
100M
1406 G08
1M
10M 20M
SAMPLING FREQUENCY (Hz)
1406 G09
U
U
U
5
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