1066 MHz RDRAM
®
Advance Information
Overview
The RDRAM® device is a general purpose high-
performance memory device suitable for use in a broad
range of applications including computer memory,
graphics, video, and any other application where high
bandwidth and low latency are required.
The 256/288 Mb RDRAM devices are extremely high-
speed CMOS DRAMs organized as 16M words by 16
or 18 bits. The use of Rambus Signaling Level (RSL)
technology permits 600 MHz to 1066 MHz transfer
rates while using conventional system and board
design technologies. RDRAM devices are capable of
sustained data transfers at 0.9375 ns per two bytes (7.5
ns per sixteen bytes).
The architecture of the RDRAM devices allows the
highest sustained bandwidth for multiple, simulta-
neous randomly addressed memory transactions. The
separate control and data buses with independent row
and column control yield over 95% bus efficiency. The
RDRAM devices four banks support up to four simul-
taneous transactions.
System-oriented features for mobile, graphics and
large memory systems include power management,
byte masking, and x18 organization. The two data bits
in the x18 organization are general and can be used for
additional storage and bandwidth or for error correc-
tion.
256/288 Mb (4Mx16/18x4i)
Figure 1: 1066 MHz RDRAM® CSP Package
The 256/288 Mb RDRAM devices are offered in a CSP
horizontal package suitable for desktop as well as low-
profile add-in card and mobile applications.
Key Timing Parameters/Part Numbers
Organization
a
4Mx16x4i
4Mx16x4i
4Mx16x4i
4Mx16x4i
I/O Freq. Core Access Time
MHz
(ns)
600
800
800
1066
1066
600
800
800
1066
1066
53
45
40
35
30
53
45
40
35
30
Part
Number
256Mi-53-600
256Mi-45-800
256Mi-45-800
256Mi-35-1066
256Mi-30-1066
288Mi-53-600
288Mi-45-800
288Mi-40-800
288Mi-35-1066
288Mi-30-1066
Features
s
4Mx16x4i
4Mx18x4i
4Mx18x4i
4Mx18x4i
4Mx18x4i
4Mx18x4i
Highest sustained bandwidth per DRAM device
- 2.1 GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 4 banks: four transactions can take place simul-
taneously at full bandwidth data rates
Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
Advanced power management:
- Multiple low power states allows flexibility in
power consumption versus time to transition to
active state
- Power-down self-refresh
Organization: 2 KB pages and 4 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
- x16 organization for low cost applications
Uses RSL for up to 1066 MHz operation
s
a. The bank designations are described in a later section. Refer
to Section "Row and Column Cycle Description" on page 17.
4i - 4 banks which use an “independent” bank architecture.
“1.8V” appended to the part number indicates the VDD supply
voltage.
s
Related Documentation
Datasheets for the RDRAM memory system components are avail-
able on the Rambus website at
www.rdram.com.
Please obtain the
"Documentation Change History"for this datasheet. The DCH is an
integral part of the data sheet and contains the most recent informa-
tion about changes made to the published version. Check the
RDRAM website regularly for the latest DCH and datasheet updates.
s
s
Document DL-0119-030
Version 0.3
Advance Information
Page 1
1066 MHz RDRAM 256/288 Mb (4Mx16/18x4i)
Pinouts and Definitions
Center-Bonded Devices - Preliminary
This table shows the pin assignments of the center-
bonded RDRAM package. The mechanical dimensions
of this package are shown in a later section. Refer to
Section "Center-Bonded uBGA Package (16x6)" on
page 63.
Table 1: Center Bonded Device (top view)
10
9
8
7
6
5
4
3
2
1
A
VDD
GND
GND
VDD
GND
GND
GND
GND
GND
VDD
GND
VDD
GND
GND
DQA6 DQA4 DQA2 DQA0
SCK
VCMOS
VDD
GND
VDD
GND
VDD
VDD
VDD
VDD
GND
VDD
GND
VDD
VDD
DQA8
CMD
VDD
GND
GNDa GNDa
CTM
VDD
CTM
VDD
GND
GND
VDD
COL1
VDD
GND
GND
VCMOS
VDD
GND
VDD
DQA7 DQA5 DQA3 DQA1
ROW2 ROW0 COL3
DQB1 DQB3 DQB5 DQB7 DQB8
CFM
GND
CFM
VDDa
ROW1 COL4
VREF
GND
COL2
VDD
COL0
GND
DQB0 DQB2 DQB4 DQB6
GND
VDD
SIO0
SIO1
GND
GND
GND
VDD
GND
VDD
B
C
D
E
F
G
H
J
K
L
M
N
P
R
S
T
U
Note the following:
s
This is the “Top View” (balls facing down, back-
side of chip facing up).
Pin #1 designation is at location A1.
Columns “A” and “U”, and Rows “1” and “10”
can be deleted when die size shrink to the point
that those balls will not fall within the die bound-
aries.
For 32Mx8 devices either DQA8 & DQB8 must be
defined as no connects or columns “B” and “T”
must be deleted completely.
s
s
s
Page 2
Advance Information
Document DL-0119-030 Version 0.3
1066 MHz RDRAM 256/288 Mb (4Mx16/18x4i)
Table 2: Pin Description
Signal
SIO1,SIO0
I/O
I/O
Type
CMOS
a
# Pins
edge
2
# Pins
center
2
Description
Serial input/output. Pins for reading from and writing to the control
registers using a serial access protocol. Also used for power man-
agement.
Command input. Pins used in conjunction with SIO0 and SIO1 for
reading from and writing to the control registers. Also used for
power management.
Serial clock input. Clock source used for reading from and writing to
the control registers
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
Data byte A. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQA8 is not used by
RDRAM devices with a x16 organization.
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Negative polarity
Logic threshold reference voltage for RSL signals
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Negative polarity.
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Positive polarity.
Row access control. Three pins containing control and address
information for row accesses.
Column access control. Five pins containing control and address
information for column accesses.
Data byte B. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM device. DQB8 is not used by
RDRAM devices with a x16 organization.
CMD
I
CMOS
a
1
1
SCK
V
DD
V
DDa
V
CMOS
GND
GNDa
DQA8..DQA0
I
CMOS
a
1
14
2
2
19
2
1
6
1
2
9
1
9
I/O
RSL
b
9
CFM
CFMN
V
REF
CTMN
CTM
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
DQB8..
DQB0
I
I
RSL
b
RSL
b
1
1
1
1
1
1
1
1
3
5
9
I
I
I
I
I/O
RSL
b
RSL
b
RSL
b
RSL
b
RSL
b
1
1
3
5
9
Total pin count per package
74
54
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Document DL-0119-030
Version 0.3
Advance Information
Page 3
1066 MHz RDRAM 256/288 Mb (4Mx16/18x4i)
DQB8..DQB0
9
RQ7..RQ5 or
ROW2..ROW0
3
RCLK
1:8 Demux
CTM CTMN
SCK,CMD
2
SIO0,SIO1
2
CFM CFMN
RQ4..RQ0 or
COL4..COL0
5
DQA8..DQA0
9
RCLK
1:8 Demux
TCLK
RCLK
Control Registers
6
REFR
Power Modes
Packet Decode
ROWR
ROWA
11
5
2
12
ROP DR
AV
Match
COLX
5
2
DX
Packet Decode
COLC
5
5
2
7
BX COP DC
S
Match
8
C
COLM
8
BR
R
DEVID
XOP
M
BC
MB MA
Mux
Row Decode
Match
DM
PRER
ACT
DRAM Core
4096x128x144
XOP Decode
Write
Buffer
Mux
Mux
PREX
Column Decode & Mask
Sense Amp
128x72
Internal DQB Data Path
PREC
RD, WR
Internal DQA Data Path
72
72
SAmp
128x72
72
RCLK
9
9
Bank 1
Bank 0
Bank 2
Bank 3
128x72
SAmp
0
0
72
9
9
RCLK
Write Buffer
Write Buffer
1:8 Demux
1:8 Demux
9
Bank 5
Bank 1
Bank 6
Bank 7
9
SAmp
SAmp
SAmp
1
1
TCLK
9
Bank 9
Bank 2
Bank 10
Bank 11
SAmp
9
2
2
TCLK
8:1 Mux
9
9
8:1 Mux
Bank 13
Bank 3
Bank 14
Bank 15
Figure 2: 256/288 Mb (4Mx16/18x4i) RDRAM Block Diagram
Document DL-0119-030 Version 0.3
SAmp
SAmp
3
3
Page 4
Advance Information
1066 MHz RDRAM 256/288 Mb (4Mx16/18x4i)
General Description
Figure 2 is a block diagram of the 256/288 Mb RDRAM
device. It consists of two major blocks: a “core” block
built from banks and sense amps similar to those
found in other types of DRAM, and a RDRAM inter-
face block which permits an external controller to
access this core at up to 1.6GB/s.
ROW Pins:
The principle use of these three pins is to
manage the transfer of data between the banks and the
sense amps of the RDRAM device. These pins are de-
multiplexed into a 24-bit ROWA (row-activate) or
ROWR (row-operation) packet.
COL Pins:
The principle use of these five pins is to
manage the transfer of data between the DQA/DQB
pins and the sense amps of the RDRAM device. These
pins are de-multiplexed into a 23-bit COLC (column-
operation) packet and either a 17-bit COLM (mask)
packet or a 17-bit COLX (extended-operation) packet.
Control Registers:
The CMD, SCK, SIO0, and SIO1
pins appear in the upper center of Figure 2. They are
used to write and read a block of control registers.
These registers supply the RDRAM device configura-
tion information to a controller and they select the
operating modes of the device. The REFR value is used
for tracking the last refreshed row. Most importantly,
the five bit DEVID specifies the device address of the
RDRAM device on the Channel.
ACT Command:
An ACT (activate) command from
an ROWA packet causes one of the 4096 rows of the
selected bank to be loaded to its associated sense amps
(one 1kbyte sense amp for DQA and one for DQB).
PRER Command:
A PRER (precharge) command
from an ROWR packet causes the selected bank to
release its associated sense amp, permitting a different
row in that bank to be activated.
Clocking:
The CTM and CTMN pins (Clock-To-
Master) generate TCLK (Transmit Clock), the internal
clock used to transmit read data. The CFM and CFMN
pins (Clock-From-Master) generate RCLK (Receive
Clock), the internal clock signal used to receive write
data and to receive the ROW and COL pins.
RD Command:
The RD (read) command causes one
of the 128 dualocts of one of the sense amps to be trans-
mitted on the DQA/DQB pins of the Channel.
DQA,DQB Pins:
These 18 pins carry read (Q) and
write (D) data across the Channel. They are multi-
plexed/de-multiplexed from/to two 72-bit data paths
(running at one-eighth the data frequency) inside the
RDRAM device.
WR Command:
The WR (write) command causes a
dualoct received from the DQA/DQB data pins of the
Channel to be loaded into the write buffer. There is also
space in the write buffer for the BC bank address and C
column address information. The data in the write
buffer is automatically retired (written with optional
bytemask) to one of the 128 dualocts of one of the sense
amps during a subsequent COP command. A retire can
take place during a RD, WR, or NOCOP to another
device, or during a WR or NOCOP to the same device.
The write buffer will not retire during a RD to the same
device. The write buffer reduces the delay needed for
the internal DQA/DQB data path turn-around.
Banks:
The 32 MB core of the RDRAM device is
divided into 4 8.0Mbyte banks, each organized as 4096
rows, with each row containing 128 dualocts, and each
dualoct containing 16 bytes. A dualoct is the smallest
unit of data that can be addressed.
Sense Amps:
The RDRAM device contains 4 sense
amps. Each sense amp consists of 2kbyte of fast storage
(1kbyte for DQA and 1kbyte for DQB) and can hold
one row of one bank of the RDRAM device. The sense
amp may hold any of the 4096 rows of an associated
bank.
PREC Precharge:
The PREC, RDA and WRA
commands are similar to NOCOP, RD and WR, except
that a precharge operation is performed at the end of
the column operation. These commands provide a
second mechanism for performing precharge.
RQ Pins:
These pins carry control and address infor-
mation. They are broken into two groups. RQ7..RQ5
are also called ROW2..ROW0, and are used primarily
for controlling row accesses. RQ4..RQ0 are also called
COL4..COL0, and are used primarily for controlling
column accesses.
PREX Precharge:
After a RD command, or after a
WR command with no byte masking (M=0), a COLX
packet may be used to specify an extended operation
(XOP). The most important XOP command is PREX.
This command provides a third mechanism for
performing precharge.
Document DL-0019-030
Version 0.3
Advance Information
Page 5
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