Supertex inc.
10-Channel, Serial-Input
Latched Display Driver
Features
►
►
►
►
►
►
►
►
►
►
High output voltage 80V
High speed 5MHz @5.0V
DD
Low power I
BB
≤ 0.1mA (all high)
Active pull down 100µA min @25
O
C
Output source current 25mA @60V V
BB
Each device drives 10 lines
High-speed serially-shifted data input
5.0V CMOS-compatible inputs
Latches on all driver outputs
Pin-compatible replacement for UCN5810A and
TL4810A, TL4810B
HV6810
General Description
The HV6810 is a monolithic integrated circuit designed
to drive a dot matrix or segmented vacuum fluorescent
display (VFD). These devices feature a serial data output to
cascade additional devices for large displays.
A 10-bit data word is serially loaded into the shift register
on the positive-going transition of the clock. Parallel data
is transferred to the output buffers through a 10-bit D-type
latch while the latch enable input is high, and is latched
when the latch enable is low. When the blanking input is
high, all of the outputs are low.
Outputs are structures formed by double-diffused MOS
(DMOS) transistors with output voltage ratings of 80V and
25mA source-current capability. All inputs are compatible
with CMOS levels.
Applications
► High speed dot matrix print head driver
►
VFD (vacuum fluorescent display) driver
Functional Block Diagram
Blanking
Latch Enable
Shift Register
Data Input
Clock
Latches
C2
2D
V
BB
1D
C1
LC1
Q1
1D
C1
C2
2D
LC2
Q2
6 Stages
(Q3 thru Q8
not shown
•
•
•
•
•
•
1D
C1
•
•
•
C2
2D
•
•
•
•
•
•
LC9
Q9
1D
C1
C2
2D
LC10
Q10
Serial
Out
Logic Diagram (positive logic)
Supertex inc.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
HV6810
Ordering Information
Package Options
Device
.353x.353in body
.180in height (max)
.050in pitch
Pin Configuration
1
2
20
20-Lead PLCC
12.80x7.50mm body
2.65mm height (max)
1.27mm pitch
20-Lead SOW
1
20
HV6810
HV6810PJ-G
HV6810WG-G
-G indicates package is RoHS compliant (‘Green’)
20-Lead PLCC (PJ)
(top view)
20-Lead SOW (WG)
(top view)
Absolute Maximum Ratings
1
Parameter
Logic supply voltage, V
DD
Output voltage
Input voltage
1
2
Product Marking
Top Marking
Value
7.5V
90V
90V
-0.3V to V
DD
+ 0.3V
YYWW AAA
LLLLLLLLLL
HV6810PJ
Driver supply voltage, V
BB
2
Bottom Marking
CCCCCCCCCCC
YY = Year Sealed
WW = Week Sealed
L = Lot Number
A = Assembler ID
C = Country of Origin*
= “Green” Packaging
*May be part of top marking
Continuous total power dissipation at
25
O
C free-air temperature:
3
20-Lead PLCC (PJ)
1
20-Lead SOW (WG)
1
Operating temperature range
Package may or may not include the following marks: Si or
1500mW
1500mW
1
-45°C +85°C
20-Lead PLCC (PJ)
Top Marking
H V 6810 WG
YYWW AAA
LLLLLLLLLL
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated
in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability. All voltages are referenced to GND.
Notes:
1. Over operating free-air temperature
2. All voltages are referenced to V
SS
3. For operation above 25
O
C ambient derate linearly to 85
O
C at 15mW/
O
C
Bottom Marking
CCCCCCCCCCC
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
L = Lot Number
C = Country of Origin*
= “Green” Packaging
* May be part of top marking
Package may or may not include the following marks: Si or
20-Lead SOW (WG)
Recommended Operating Conditions
Sym
V
DD
V
BB
V
SS
V
IH
V
IL
I
OH
f
CLK
T
A
Parameter
Supply voltage
High supply voltage
Supply voltage
High-level input voltage (for V
DD
= 5.0V)
Low-level input voltage
Continuous high-level Q output current
Clock frequency
Operating ambient temperature
Min
4.5
20
-
3.5
-0.3
25
-
-40
Typ
-
-
0
-
-
-
-
-
Max
5.5
80
-
5.3
0.8
-
5.0
+85
Units
V
V
V
V
V
mA
MHz
°C
Conditions
---
---
---
---
---
---
---
---
Supertex inc.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
2
HV6810
DC Electrical Characteristics
Sym
V
OH
Parameter
High level output voltage
Q outputs
Serial output
Q outputs
Serial output
Low level Q output current (pull-down current)
Off-state output current
High level input current
Supply current from V
DD
(standby)
(V
DD
= 5.0V, V
BB
= 60V, V
SS
= 0V, T
A
= 25
O
C unless otherwise noted)
Min
57.5
4.0
-
-
60
-
-
-
Typ
58
4.5
0.15
0.05
80
-1.0
Max
-
-
1.0
0.1
-
-15
1.0
Units
V
Conditions
I
O
= +25mA
V
DD
= +4.5V, I
OL
= +100µA
I
O
= -100µA,
blanking input at V
DD
V
DD
= +4.5V, I
O
= -100µA
T
A
= Max, V
OL
= +0.7V
V
O
= 0V, blanking input at V
DD
V
lN
= V
DD
All inputs at 0V,
one Q output high
All inputs at 0V,
all Q outputs low
All outputs low,
all Q outputs open
All outputs high,
all Q outputs open
V
OL
I
OL
I
O(OFF)
I
IH
I
DD
Low level output voltage
V
µA
µA
µA
µA
10
10
0.05
0.05
50
50
0.1
mA
0.1
-
-
I
BB
Supply current from V
BB
-
* All typical values are at T
A
= 25
O
C except for I
OL
and I
O(OFF)
.
AC Electrical Characteristics
Sym
t
W(CKH)
t
W(LEH)
t
SU(D)
t
H(D)
t
CKH-LEH
t
PD*
Parameter
Pulse duration, clock high
(Timing requirements over recommended operating conditions)
Min
100
100
50
50
50
-
Typ
-
-
-
-
-
300
Max
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
Conditions
---
---
---
---
---
---
Pulse duration, latch enable high
Setup time, data before clock
Hold time, data after clock
Delay time, clock to latch enable high
Propagation delay time, latch enable to output
* Switching characteristics, V
BB
= 60V, T
A
= 25
O
C
Power-up sequence should be the following:
1. Connect ground V
SS
2. Apply V
DD
3. Set all inputs (Data, CLK, Enable, etc.) to a known state
4. Apply V
BB
The V
BB
should not drop below V
DD
or float during operation.
Power-down sequence should be the reverse of the above.
Supertex inc.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
3
HV6810
Switching Waveforms
t
W(CKH)
V
IH
Clock
50%
50%
V
IL
t
SU(D)
Valid
t
H(D)
V
IH
50%
V
IL
Clock
Input
50%
Valid
t
CKH-LEH
50%
t
PD
90%
Valid
t
W(LEH)
50%
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
Latch
Enable
Q Output
Data
50%
Input Timing
Output Switching Timing
Timing Diagram
Clock
Data In
VALID
IRRELEVANT
SR Contents
INVALID
VALID
Latch
Enable
Latch
Contents
PREVIOUSLY STORED DATA
NEW DATA VALID
Blanking
Q Outputs
VALID
Supertex inc.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
4
HV6810
Input and Output Equivalent Circuits
VDD
VBB
DATA
INPUT
DATA
OUT
VSS
VSS
Input Equivalent Circuit
Logic Data Output
Function Table
Serial
Data
Input
H
L
X
---
---
Clock
Input
Shift Register
Contents
I
1
I
2
I
3
... I
N-1
I
N
H R
1
R
2
... R
N-2
R
N-1
L R
1
R
2
... R
N-2
R
N-1
R
1
R
2
R
3
... R
N-1
R
N
X X X ... X
---
X
P
1
P
2
P
3
... P
N-1
P
N
Serial
Data
Output
R
N-1
R
N-1
R
N
X
P
N
---
L
H
---
R
1
R
2
R
3
... R
N-1
R
N
P
1
P
2
P
3
... P
N-1
P
N
X X X ... X
X
L
H
P
1
P
2
P
3
... P
N-1
P
N
L L L ... L
L
---
---
---
---
LE
Strobe
Input
Latch Contents
I
1
I
2
I
3
... I
N-1
I
N
Blanking
Input
Output Contents
I
1
I
2
I
3
... I
N-1
I
N
Notes:
L = Low logic level, H = High logic level, X = Don’t care, P = Present state, R = Previous state
= Low to high transition
= High to low transition
Supertex inc.
●
1235 Bordeaux Drive, Sunnyvale, CA 94089
●
Tel: 408-222-8888
●
www.supertex.com
5
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