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GTLP8T306MTCX_NL

产品描述Bus Transceiver, GTLP Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, 4.40 MM, MO-153, TSSOP-24
产品类别逻辑    逻辑   
文件大小55KB,共6页
制造商Fairchild
官网地址http://www.fairchildsemi.com/
标准
下载文档 详细参数 全文预览

GTLP8T306MTCX_NL概述

Bus Transceiver, GTLP Series, 1-Func, 8-Bit, True Output, CMOS, PDSO24, 4.40 MM, MO-153, TSSOP-24

GTLP8T306MTCX_NL规格参数

参数名称属性值
是否Rohs认证符合
厂商名称Fairchild
零件包装代码TSSOP
包装说明4.40 MM, MO-153, TSSOP-24
针数24
Reach Compliance Codecompliant
控制类型COMMON CONTROL
计数方向BIDIRECTIONAL
系列GTLP
JESD-30 代码R-PDSO-G24
JESD-609代码e3
长度7.8 mm
逻辑集成电路类型BUS TRANSCEIVER
最大I(ol)0.05 A
湿度敏感等级1
位数8
功能数量1
端口数量2
端子数量24
最高工作温度85 °C
最低工作温度-40 °C
输出特性3-STATE
输出极性TRUE
封装主体材料PLASTIC/EPOXY
封装代码TSSOP
封装等效代码TSSOP24,.25
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法TAPE AND REEL
峰值回流温度(摄氏度)260
电源3.3 V
Prop。Delay @ Nom-Sup8.3 ns
传播延迟(tpd)8.3 ns
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.45 V
最小供电电压 (Vsup)3.15 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级INDUSTRIAL
端子面层Matte Tin (Sn)
端子形式GULL WING
端子节距0.65 mm
端子位置DUAL
处于峰值回流温度下的最长时间NOT SPECIFIED
翻译GTL/P & LVTTL
宽度4.4 mm
Base Number Matches1

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GTLP8T306 8-Bit LVTTL/GTLP Bus Transceiver
September 1997
Revised December 2000
GTLP8T306
8-Bit LVTTL/GTLP Bus Transceiver
General Description
The GTLP8T306 is an 8-bit bus transceiver that provides
LVTTL to GTLP signal level translation. The device pro-
vides a high speed interface between cards operating at
LVTTL logic levels and a backplane operating at GTLP
logic levels. High speed backplane operation is a direct
result of GTLP’s reduced output swing (
<
1V), reduced input
threshold levels and output edge rate control. The edge
rate control minimizes bus settling time. GTLP is a Fairchild
Semiconductor derivative of the Gunning Transceiver logic
(GTL) JEDEC standard JESD8-3.
Fairchild’s GTLP has internal output edge-rate control and
is process, voltage, and temperature (PVT) compensated.
Its function is similar to BTL and GTL but with different out-
put levels and receiver thresholds. The GTLP output LOW
level is typically less than 0.5V, the output HIGH level is
1.5V and the receiver threshold is 1.0V.
Features
s
Bidirectional interface between GTLP and LVTTL logic
levels
s
Designed with edge rate control circuitry to reduce out-
put noise on the GTLP port
s
V
REF
pin provides external supply reference voltage for
receiver threshold adjustibility
s
Special PVT Compensation circuitry to provide consis-
tent performance over variations of process, supply volt-
age and temperature
s
TTL compatible driver and control inputs
s
Designed using Fairchild advanced CMOS technology
s
Bushold data inputs on A port to eliminate the need for
external pull-up resistors for unused inputs
s
Power up/down and power off high impedance for live
insertion
s
5V over voltage tolerance on LVTTL ports
s
Open drain on GTLP to support wired-or connection
s
Flow through pinout optimizes PCB layout
s
A Port source/sink
24mA/
+
24mA
s
B Port sink
+
50mA
Ordering Code:
Order Number
GTLP8T306MTC
Package Number
MTC24
Package Description
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS500051
www.fairchildsemi.com

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