7c198: 10/25/89
Revision: February 29, 1996
Features
D
D
D
D
D
D
D
High speed
15 ns
CMOS for optimum speed/power
Low active power
990 mW
Low standby power
195 mW
Easy memory expansion with CE and
OE features
TTL compatible inputs and outputs
Automatic power down when
deselected
The CY7C198 is a high performance
CMOS static RAM organized as 32,768
words by8bits.Easymemoryexpansionis
provided by an active LOW chip enable
(CE)andactiveLOWoutputenable(OE)
and three state drivers. This device has an
automatic power down feature, reducing
the power consumption by 80% when de
selected. The CY7C198 is available in a
600 mil wide cerDIP and LCC package
and a 32 lead TSOP package.
An active LOW write enable signal (WE)
controls the writing/reading operation of
the memory. When CE and WE inputs
arebothLOW,dataontheeightdatainput/
Functional Description
output pins (I/O
0
through I/O
7
) is written
intothememorylocationaddressedbythe
address present on the address pins (A
0
through A
14
). Reading the device is ac
complishedbyselectingthedeviceanden
abling the outputs, CE and OE active
LOW, while WE remains inactive or
HIGH. Under these conditions, the con
tents of the location addressed by the in
formationonaddresspinsispresentonthe
eight data input/output pins.
Theinput/outputpinsremaininahigh im
pedance state unless the chip is selected,
outputs are enabled, and write enable
(WE) is HIGH.
A die coat is used to ensure alpha immunity.
32K x 8 Static RAM
CY7C198
Logic Block Diagram
Pin Configurations
CerDIP
Top View
A
5
A
6
A
7
A
8
A
9
A
10
I/O
0
A
11
A
12
I/O
1
A
13
A
14
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
4
5
6
7
8
9
10
11
12
13
A7
A 12
A 14
V
CC
LCC
Top View
3
2
1 32 31 30
29
28
27
26
25
24
23
22
21
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
WE
NC
A
13
C198 1
INPUT BUFFER
A
0
ROW DECODER
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
I/O
0
I/O
2
SENSE AMPS
I/O
1
I/O
2
I/O
3
GND
14 15 16 17 1819 20
GND
I/O
1
I/O
2
NC
I/O
3
I/O
4
I/O
5
1024 x 32 x 8
ARRAY
C198 3
I/O
4
I/O
5
CE
WE
COLUMN
DECODER
OE
POWER
DOWN
I/O
6
I/O
7
A
10
A
11
A
12
A
13
A
14
C198 2
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA) Commercial
Military
Maximum Standby Current (mA)
7C198-15 7C198-20 7C198-25 7C198-35 7C198-45
15
Shaded area contains preliminary information.
Cypress Semiconductor Corporation
180
30
20
150
170
30
25
35
45
150
30
150
25
150
25
D
3901 North First Street
1
D
San Jose
CA 95134
D
408-943-2600
February 1988 - Revised February 1996
D
7c198: 10/25/89
Revision: February 29, 1996
CY7C198
Pin Configurations
(continued)
OE
A
1
A
2
A
3
A
4
WE
V
CC
NC
NC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP
Top View
32
21
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
NC
NC
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12
C198 4
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines,
not tested.)
Storage Temperature . . . . . . . . . . . . . . . . . . . -65
_
C to +150
_
C
Ambient Temperature with
Power Applied . . . . . . . . . . . . . . . . . . . . . . . . -55
_
C to +125
_
C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[15]
. . . . . . . . . . . . . . . . . . -0.5V to V
CC
+ 0.5V
DC Input
Voltage
[15]
. . . . . . . . . . . . . . . . -0.5V to V
CC
+ 0.5V
Output Current into Outputs (LOW) . . . . . . . . . . . . . . . 20 mA
Notes:
15. V
IL
(min.) = -2.0V for pulse durations less than 20 ns.
16. T
A
is the instant on" case temperature.
Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . >2001V
(per MIL STD 883, Method 3015)
Latch Up Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200 mA
Operating Range
Range
Commercial
Military
[16]
Ambient
Temperature
0
_
C to +70
_
C
-55
_
C to +125
_
C
V
CC
5V ± 10%
5V ± 10%
2
7c198: 10/25/89
Revision: February 29, 1996
CY7C198
Electrical Characteristics
Over the Operating Range
[17]
7C198-15
Parameter
V
OH
Description
Output HIGH
V
oltage
V
OL
Output LOW
V
oltage
V
IH
Input HIGH
V
oltage
Test Conditions
V
CC
= Min.,
I
OH
= -4.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
2.2
V
CC
+0.3V
-0.5
0.8
0.4
Min.
2.4
Max.
7C198-20
Min.
2.4
Max.
7C198-25
Min.
2.4
Max.
7C198-35, 45
Min.
2.4
Max.
Unit
V
0.4
0.4
0.4
V
2.2
V
CC
+0.3V
2.2
V
CC
2.2
V
CC
V
V
IL
Input LOW
V
oltage
[15]
-0.5
0.8
-0.5
0.8
-0.5
0.8
V
I
IX
I
OZ
Input Load Current
Output Leakage
Current
GND < V
I
< V
CC
GND < V
O
< V
CC
,
Output Disabled
V
CC
= Max.,
-5
-5
+5
+5
-5
-5
+5
+5
-5
-5
+5
+5
-5
-5
+5
+5
m
A
m
A
mA
I
OS
Output Short
Circuit Current
[18]
-300
-300
-300
-300
V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0
mA
mA,
Mil
180
170
150
150
Com'l
150
mA
I
CC
V
CC
Operating
Supply Current
f = f
MAX
= 1/t
RC
I
SB1
Automatic CE
Power Down
Current
Inputs
I
SB2
Automatic CE
Power Down
Current
Inputs
CMOS
Max. V
CC
,
TTL
Max. V
CC
, CE > V
IH
,
V
IN
> V
IH
or V
IN
< V
IL
, f = f
MAX
30
30
30
25
mA
15
15
15
15
mA
CE > V
CC
- 0.3V
V
IN
> V
CC
- 0.3V or
,
V
IN
< 0.3V f = 0
Shaded area contains preliminary information
Capacitance
[19]
Parameter
C
IN
C
OUT
Notes:
17.
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
Max.
10
10
Unit
pF
pF
_
C, f = 1 MHz,
V
CC
= 5.0V
5 0V
See the last page of this specification for Group A subgroup testing in
formation.
19.
T
ested initially and after any design or process changes that may affect
these parameters.
18.
Not more than one output should be shorted at one time. Duration of
the short circuit should not exceed 30 seconds.
3
7c198: 10/25/89
Revision: February 29, 1996
CY7C198
AC Test Loads and Waveforms
[20]
5V
OUTPUT
R1 481
W
5V
OUTPUT
R1 481
W
3.0V
GND
10%
< f
r
R2
R2
5 pF
30 pF
255
W
255
W
INCLUDING
INCLUDING
JIG AND
JIG AND
C198 5
SCOPE
(b)
SCOPE
(a)
Equivalent to:
THÉVENIN EQUIVALENT
167
W
OUTPUT
1.73V
Switching Characteristics
Over the Operating Range
[17, 21]
7C198-15
Parameter
READ CYCLE
Description
Min.
Max.
7C198-20
Min.
Max.
ALL INPUT PULSES
90%
90%
10%
< t
r
C198 6
7C198-25
Min.
Max.
7C198-35
Min.
Max.
7C198-45
Min.
Max.
Unit
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[22]
OE HIGH to High Z
[22, 23]
CE LOW to Low Z
[22]
CE HIGH to High Z
[22, 23]
CE LOW to Power Up
CE HIGH to Power Down
[24, 25]
15
3
0
3
0
15
10
10
0
0
9
9
0
3
15
15
7
7
7
15
20
3
0
3
0
20
15
15
0
0
15
10
0
3
20
20
9
9
9
20
25
3
3
3
0
25
20
20
0
0
20
15
0
3
25
25
10
11
11
20
35
3
3
3
0
35
22
30
0
0
22
15
0
3
35
35
16
15
15
20
45
3
3
3
0
45
22
40
0
0
22
15
0
3
45
45
16
15
15
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
Shaded area contains preliminary information.
Notes:
Write Cycle Time
CE LOW to Write End
Address Set Up to Write End
Address Hold from Write End
Address Set Up to Write Start
WE Pulse Width
Data Set Up to Write End
Data Hold from Write End
WE LOW to High Z
[23]
WE HIGH to Low Z
[22]
7
10
11
15
15
20 t
r
3 ns for the 15 ns and 20 ns speeds, t
r
5 ns for the 20 ns and
slower speeds.
21. Test conditions assume signal transition time of 3 ns or less for the
12 ns and15 ns speeds and 5 ns for the 20 ns andslowerspeeds,timing
referencelevelsof1.5V,inputpulselevelsof0to3.0V,andoutputload
ing of the specified I
OL
/I
OH
and 30 pF load capacitance.
22. At any given temperature and voltage condition, t
HZCE
is less than
t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any
given device.
23. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b)
of AC Test Loads. Transition is measured ±500 mV from steady state
voltage.
24. The internal write time of the memory is defined by the overlap of CE
LOW and WE LOW. Both signals must be LOW to initiate a write and
either signal can terminate a write by going HIGH. The data input set
upandholdtimingshouldbereferencedtotherisingedgeofthesignal
that terminates the write.
25. The minimum write cycle time for write cycle #3 (WE controlled, OE
LOW) is the sum of t
HZWE
and t
SD
.
4
7c198: 10/25/89
Revision: February 29, 1996
CY7C198
Switching Waveforms
Read Cycle No. 1
[26, 27]
t
RC
ADDRESS
DATA OUT
Read Cycle No. 2
[27, 28]
t
OHA
PREVIOUS DATA VALID
t
AA
DATA VALID
C198 7
CE
OE
t
ACE
t
LZOE
HIGH IMPEDANCE
t
LZCE
t
PU
50%
t
DOE
t
RC
t
HZOE
t
HZCE
DATA VALID
t
PD
50%
DATA OUT
V
CC
SUPPLY
CURRENT
HIGH
IMPEDANCE
ICC
ISB
C198 8
Write Cycle No. 1 (WE Controlled)
[24, 29, 30]
t
WC
ADDRESS
CE
WE
OE
DATA I/O
t
HZOE
Notes:
26.
27.
28.
Device is continuously selected. OE, CE = V
IL
.
WE is HIGH for read cycle.
.
Address valid prior to or coincident with CE transition LOW
29.
30.
Data I/O is high impedance if OE = V
IH
.
If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state.
t
SA
t
AW
t
PWE
t
HA
t
SD
DATA
IN
VALID
t
HD
C198 9
5
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