Advanced v0.2
™
ProASIC3E Flash Family FPGAs
Features and Benefits
High Capacity
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600 k to 3 Million System Gates
108 k to 504 kbits of True Dual-Port SRAM
Up to 616 User I/Os
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
Live-At-Power-Up Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered-Off
1 kbit of FlashROM (FROM)
150+ MHz Internal System Performance with 3.3 V,
66 MHz 64-bit PCI
Up to 350 MHz External System Performance
Secure ISP Using On-Chip 128-Bit AES Decryption via
JTAG (IEEE1532-compliant)
FlashLock™ to Secure FPGA Contents
1.5 V Core Voltage for Low Power
Support for 1.5-V-Only Systems
Low-Impedance Flash Switches
Segmented, Hierarchical Routing and Clock Structure
Ultra-Fast Local and Long-Line Network
Enhanced High-Speed, Very Long-Line Network
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
Pro (Professional) I/O
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700 Mbps DDR, LVDS-Capable I/Os
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages – Up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS
2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL and LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V,
GTL 2.5 V / 3.3 V, HSTL Class 1 and 2, SSTL2 Class 1 and 2,
SSTL3 Class 1 and 2
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay, Weak Pull-Up/Down
Schmitt-Trigger Option on Single-Ended Inputs
Weak Pull-Up/Down
IEEE1149.1 (JTAG) Boundary-Scan Test
Pin-Compatible Packages Across the ProASIC3E Family
Six CCC Blocks, Each with an Integrated PLL
Flexible Phase Shift, Multiply/Divide, and Delay
Capabilities
Wide Input Frequency Range (1.5 MHz to 350 MHz)
Variable-Aspect Ratio 4,608-bit RAM Blocks (x1, x2, x4,
x9, x18 Organizations Available)
True Dual-Port SRAM (except x18)
24 SRAM and FIFO Configurations with Synchronous
Operation up to 350 MHz
Programmable Embedded FIFO Control Logic
Reprogrammable Flash Technology
On-Chip User Nonvolatile Memory
Performance
Clock Conditioning Circuit (CCC) and PLL
In-System Programming (ISP) and Security
Low Power
SRAMs and FIFOs
High-Performance Routing Hierarchy
Table 1 •
ProASIC3E Product Family
A3PE600
600 k
13,824
108
24
1k
Yes
6
18
8
270
PQ208
FG256, FG484
A3PE1500
1.5 M
38,400
270
60
1k
Yes
6
18
8
439
PQ208
FG484, FG676
A3PE3000
3M
75,264
504
112
1k
Yes
6
18
8
616
PQ208
FG484, FG896
System Gates
VersaTiles (D-Flip-Flops)
RAM kbits (1,024 bits)
4,608 Bit Blocks
FlashROM (FROM) Bits
Secure (AES) ISP
CCCs with Integrated PLLs
1
VersaNet Globals
2
I/O Banks
Maximum User I/Os
Package Pins
PQFP
FBGA
Notes:
1. The PQ208 package has six CCCs and two PLLs.
2. Six chip (main) and three quadrant global networks are available.
3. For devices supporting lower densities, refer to the
ProASIC3 Flash FPGAs
datasheet.
January 2005
© 2005 Actel Corporation
i
See Actel’s website for the latest version of the datasheet.
ProASIC3E Flash Family FPGAs
I/Os Per Package
A3PE600
Package
PQ208
FG256
FG484
FG676
FG896
Notes:
1. Each used differential I/O pair reduces the number of single-ended I/Os available by two.
2. FG256 and FG484 are footprint-compatible packages.
3. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (V
REF
) per minibank
(group of I/Os). Refer to the
"I/O Banks and I/O Standards Compatibility" on page 27
for more information about V
REF
and the use
of minibanks.
4. Advanced information subject to change.
Single-Ended
I/O
147
165
270
–
–
Differential
I/O Pairs
65
79
135
–
–
A3PE1500
Single-Ended
I/O
147
–
280
439
–
Differential
I/O Pairs
65
–
136
209
–
A3PE3000
Single-Ended
I/O
147
–
280
–
616
Differential
I/O Pairs
65
–
136
–
300
Ordering Information
A3PE3000 _
1
FG
896
I
Application (Ambient Temperature Range)
Blank = Commercial (0˚C to +70˚C)
I = Industrial (–40˚C to +85˚C)
PP = Pre-Production
ES = Engineering Silicon (Room Temperature Only)
Package Lead Count
Package Type
PQ = Plastic Quad Flat Pack (0.5 mm pitch)
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
Speed Grade
F
Blank
1
2
=
=
=
=
20% Slower than Standard*
Standard
15% Faster than Standard
25% Faster than Standard
Part Number
A3PE600 = 600,000 System Gates
A3PE1500 = 1,500,000 System Gates
A3PE3000 = 3,000,000 System Gates
Note:
*DC and switching characteristics for –F speed grade targets based only on simulation.
The characteristics provided for –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might
be added and will be reflected in future revisions of this document. The –F speed grade is only supported in commercial temperature
range.
Figure 1 •
Ordering Information
ii
A d v a n c e d v 0 .2
ProASIC3E Flash Family FPGAs
Temperature Grade Offerings
Package
PQ208
FG256
FG484
FG676
FG896
A3PE600
C, I
C, I
C, I
–
–
A3PE1500
C, I
–
C, I
C, I
–
A3PE3000
C, I
–
C, I
–
C, I
Note:
C = Commercial Temperature Range: 0°C to 70°C Ambient
I = Industrial Temperature Range: –40°C to 85°C Ambient
Speed Grade and Temperature Grade Matrix
–F
C
I
Notes:
1. C = Commercial Temperature Range: 0°C to 70°C Ambient
2. I = Industrial Temperature Range: –40°C to 85°C Ambient
3. DC and switching characteristics for –F speed grade targets based only on simulation.
The characteristics provided for –F speed grade are subject to change after establishing FPGA specifications. Some restrictions
might be added and will be reflected in future revisions of this document. The –F speed grade is only supported in commercial
temperature range.
✓
–
3
Std.
✓
✓
–1
✓
✓
–2
✓
✓
Contact your local Actel representative for device availability (http://www.actel.com/contact/offices/index.html).
A d v a n c ed v 0.2
iii
ProASIC3E Flash Family FPGAs
Table of Contents
Introduction and Overview
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Device Architecture
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
Software Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50
Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
DC and Switching Characteristics
General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63
Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-66
Embedded FROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75
JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-75
Package Pin Assignments
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Datasheet Information
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
International Traffic in Arms Regulations (ITAR) and Export Administration
Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
iv
A d va n ce d v 0 . 2
ProASIC3E Flash Family FPGAs
Introduction and Overview
General Description
ProASIC3E, the third-generation family of Actel Flash
FPGAs, offers performance, density, and features beyond
those of the ProASIC
PLUS®
family. The nonvolatile Flash
technology gives ProASIC3E devices the advantage of
being a secure, low-power, single-chip solution that is
live at power-up. ProASIC3E is reprogrammable and
offers time-to-market benefits at an ASIC-level unit cost.
These features enable designers to create high-density
systems using existing ASIC or FPGA design flows and
tools.
ProASIC3E devices offer 1 kbit of on-chip, user
nonvolatile FlashROM (FROM) memory storage as well as
clock conditioning circuitry based on six integrated
phase-locked loops (PLLs). ProASIC3E devices have up to
3 million system gates, supported with up to 504 kbits of
true dual-port SRAM and up to 616 user I/Os.
Security
The nonvolatile, Flash-based ProASIC3E devices require
no boot PROM, so there is no vulnerable external
bitstream that can be easily copied. ProASIC3E devices
incorporate FlashLock, which provides a unique
combination of reprogrammability and design security
without external overhead, advantages that only an
FPGA with nonvolatile, Flash programming can offer.
ProASIC3E devices utilize a 128-bit Flash-based lock and a
separate AES key to secure programmed intellectual
property and configuration data. In addition, all FROM
data in the ProASIC3E devices can be encrypted prior to
loading, using the industry-leading AES-128 (FIPS192) bit
block cipher encryption standard. The AES standard was
adopted by the National Institute of Standards and
Technology (NIST) in 2000, and replaces the 1977 DES
standard. ProASIC3E devices have a built-in AES
decryption engine and a Flash-based AES key that make
them the most comprehensive programmable logic
device security solution available today. ProASIC3E
devices with AES-based security allow for secure, remote
field updates over public networks such as the Internet,
and ensure that valuable IP remains out of the hands of
system overbuilders, system cloners, and IP thieves. The
contents of a programmed ProASIC3E device cannot be
read back, although secure design verification is possible.
Security, built into the FPGA fabric, is an inherent
component of the ProASIC3E family. The Flash cells are
located beneath seven metal layers, and many device
design and layout techniques have been used to make
invasive attacks extremely difficult. ProASIC3E, with
FlashLock and AES security, is unique in being highly
resistant to both invasive and noninvasive attacks. Your
valuable IP is protected and secure, making remote ISP
possible. A ProASIC3E device provides the most
impenetrable security for programmable logic designs.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low-unit
cost, performance, and ease of use. Unlike SRAM-based
FPGAs, the Flash-based ProASIC3E devices allow for all
functionality to be live at power-up; no external boot
PROM is required. On-board security mechanisms
prevent access to all the programming information and
enable secure remote updates of the FPGA logic.
Designers can perform secure remote in-system
reprogramming to support future design iterations and
field upgrades with confidence that valuable intellectual
property (IP) cannot be compromised or copied. Secure
ISP can be performed using the industry-standard AES
algorithm. The ProASIC3E family device architecture
mitigates the need for ASIC migration at higher user
volumes. This makes the ProASIC3E family a cost-
effective ASIC replacement solution, especially for
applications
in
the
consumer,
networking/
communications, computing, and avionics markets.
A d v a n c ed v 0.2
1-1
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