for sensing signals near the negative supply. The input
common mode range extends from 2.5V below the
positive supply down to the negative supply rail. Like
the LT1016, this comparator is specifically designed to
inter face directly to TTL logic with complementary
outputs. The comparator may operate from either a single
5V supply or dual ±5V supplies. Tight offset voltage
specifications and high gain allow the LT1116 to be used
in precision applications.
The LT1116 is designed for improved speed and stability
for a wide range of operating conditions. The output stage
provides active drive in both directions for maximum speed
into TTL logic or passive loads, yet it has minimal cross-
conduction current. Unlike other fast comparators, the
LT1116 remains stable even for slow transitions through
the active region, which eliminates the need to specify a
minimum input slew rate.
The LT1116 has an internal, TTL compatible latch for
retaining data at the outputs. The latch holds data as
long as the latch pin is held high. Device parameters
such as gain, offset, and negative power supply current
are not significantly affected by variations in negative
supply voltage.
applicaTions
n
n
n
n
n
n
n
n
High Speed A/D Converters
Zero Crossing Detectors
Current Sense for Switching Regulators
Extended Range V to F Converters
Fast Pulse Height/Width Discriminators
High Speed Triggers
Line Receivers
High Speed Sampling Circuits
L,
LTC, LT, and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Typical applicaTion
V
IN
100mV STEP
5mV OVERDRIVE
Comparator Response Time
THRESHOLD
Fast Current Comparator for
Current Mode Switching Regulator
LOGIC
5V
DRIVER
M1
12ns
OUTPUT
VOLTAGE V
OUT
1V/DIV
Q
LT1116
Q
+
C1
–
R1
R
SENSE
12ns
0
0
20
TIME (ns)
20
LT1116 • TA02
BLANKING
CONTROL INPUT
LT1116 • TA01
1116fc
For more information
www.linear.com/LT1116
1
LT1116
absoluTe MaxiMuM raTings
(Note 1)
Supply Voltage (V
+
) to GND ........................................7V
Negative Supply Voltage (V
–
) ....................... –7V to GND
Voltage
Differential Input Voltage .................................... ±15V
Inputs Voltage (Either Input) ...........(V
–
) –0.3V to 15V
Latch Pin Voltage .............................Equal to Supplies
Output Current (Continuous) ............................... ± 20mA
Operating Temperature Range ..................... 0°C to 70°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
pin conFiguraTion
TOP VIEW
V
+
1
+IN 2
–IN 3
V
–
4
8
Q
OUT
Q OUT
GND
LATCH
ENABLE
V
+
1
+IN 2
–IN 3
V
–
4
TOP VIEW
8
Q
OUT
Q OUT
GND
LATCH
ENABLE
+
–
7
6
5
+
–
7
6
5
N8 PACKAGE
8-LEAD PDIP
T
JMAX
= 100°C,
θ
JA
= 130°C/W
S8 PACKAGE
8-LEAD PLASTIC SO
T
JMAX
= 100°C,
θ
JA
= 160°C/W
orDer inForMaTion
TUBE
LT1116CN8#PBF
LT1116CS8#PBF
TAPE AND REEL
NA
LT1116CS8#TRPBF
PART MARKING*
1116
1116
PACKAGE DESCRIPTION
8-Lead PDIP
8-Lead Plastic SO
SPECIFIED TEMPERATURE RANGE
0°C to 70°C
0°C to 70°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.*The temperature grade is identified by a label on the shipping container.
Parts ending with PBF are RoHS and WEEE compliant.
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/.
Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
1116fc
For more information
www.linear.com/LT1116
LT1116
The
l
denotes the specifications which apply over full operating temperature
range, otherwise specifications are at T
A
= 25°C. V = 5V, V
–
= –5V, V
OUT
(Q) = 1.4V, LATCH = 0V. Specifications for V
OS
, I
B
, CMRR,
and Voltage Gain are valid for single supply operation, V
+
= 5V, V
–
= 0V, unless noted.
SYMBOL PARAMETER
V
OS
ΔV
OS
ΔT
I
OS
l
B
Input Offset Current
Input Bias Current, Sourcing
Input Voltage Range
CMRR
PSRR
A
V
I
+
I
–
V
OH
V
OL
V
IH
V
IL
I
IL
t
PD
t
PD
∆t
PD
t
SU
t
H
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Small Signal Voltage Gain
Positive Supply Current
Negative Supply Current
Output High Voltage
Output Low Voltage
+ Positive Latch Threshold
– Latch Threshold
Latch Input Current
Propagation Delay
Propagation Delay
Differential Propagation Delay
Latch Set-Up Time
Latch Hold Time
V
LATCH
= 0V
∆V
IN
= 100mV, OD = 5mV (Note 4)
l
elecTrical characTerisTics
+
Input Offset Voltage
Input Offset Voltage Drift
CONDITIONS
R
S
≤ 100Ω (Note 2)
l
l
MIN
TYP
1.0
5
MAX
±3.0
3.5
UNITS
mV
mV
µV/°C
(Note 2)
(Note 3)
Arbitrary Supply Range
Single 5V Supply
–5V ≤ V
CM
≤ 2.5V, V
S
= ±5V
0V ≤ V
CM
≤ 2.5V
Positive Supply, 4.6V ≤ V
+
≤ 5.4V
Negative Supply, –7 ≤ V
–
≤ –2V
1V ≤ V
OUT
≤ 2V
l
l
l
l
l
l
l
l
0.5
10
V
–
0
75
65
60
80
1400
90
90
75
100
3000
27
5
2.7
2.4
3.4
3.0
0.3
0.4
2.0
2
20
(V
+
) –2.5
2.5
µA
µA
V
V
dB
dB
dB
dB
V/V
l
l
38
7
mA
mA
V
V
I
SOURCE
= 1mA
I
SOURCE
= 10mA
l
SINK
= 4mA
l
SINK
= 10mA
l
l
l
l
l
l
0.5
V
V
V
V
µA
ns
ns
ns
ns
ns
ns
ns
0.8
–20
12
10
–500
16
18
14
16
3
2
2
∆V
IN
= 100mV, OD = 20mV (Note 4)
l
∆V
IN
= 100mV, OD = 5mV (Note 4)
(Note 5)
(Note 5)
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
Input offset voltage is defined as the average of two offset
voltages measured by forcing first the Q output to 1.4V then forcing
the
Q
output to 1.4V.
Note 3:
Input bias current is defined as the average of the two input
currents.
Note 4:
t
PD
and ∆t
PD
cannot be measured in automatic handling equipment
with low values of overdrive. The LT1116 is sample tested with a 1V step
and 500mV overdrive. Correlation tests have shown that t
PD
and ∆t
PD
can
be guaranteed with this test if additional DC tests are performed to verify
internal bias conditions are correct. For low overdrive conditions V
OS
is
added to the measured overdrive.
Note 5:
Input latch set-up time, t
SU
, is the interval in which the input signal
must be stable prior to asserting the latch signal. The hold time,
t
H
, is the interval after the latch is asserted in which the input signal must
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