®
ETC5054
ETC5057
SERIAL INTERFACE CODEC/FILTER
COMPLETE CODEC AND FILTERING SYS-
TEM (DEVICE) INCLUDING:
– Transmit high-pass and low-pass filtering.
– Receive low-pass filter with sin x/x correction.
– Active RC noise filters
–
µ-law
or A-law compatible COder and DECoder.
– Internal precision voltage reference.
– Serial I/O interface.
– Internal auto-zero circuitry.
A-LAW 16 PINS (ETC5057FN, 20 PINS)
µ-LAW
WITHOUT SIGNALING, 16 PINS
(ETC5054FN, 20 PINS)
MEETS OR EXCEEDS ALL D3/D4 AND
CCITT SPECIFICATIONS
±5V
OPERATION
LOW OPERATING POWER - TYPICALLY 60
mW
POWER-DOWN STANDBY MODE - TYPI-
CALLY 3 mW
AUTOMATIC POWER-DOWN
TTL OR CMOS COMPATIBLE DIGITAL IN-
TERFACES
MAXIMIZES LINE INTERFACE CARD CIR-
CUIT DENSITY
0 to 70°C OPERATION
DIP16
(Plastic)
ORDERING NUMBERS:
ETC5057N
ETC5054N
O
DESCRIPTION
The ETC5057/ETC5054 family consists of A-law
and
µ–law
monolithic PCM CODEC/filters utilizing
the A/D and D/A conversion architecture shown in
the block diagram below, and a serial PCM inter-
face. The devices are fabricated using double-
poly CMOS process. The encode portion of each
device consists of an input gain adjust amplifier,
an active RC pre-filter which eliminates very high
frequency noise prior to entering a switched-ca-
pacitor band-pass filter that rejects signals below
200 Hz and above 3400 Hz. Also included are
auto-zero circuitry and a companding coder which
samples the filtered signal and encodes it in the
companded A-law or
µ–law
PCM format. The de-
code portion of each device consists of an ex-
panding decoder, which reconstructs the analog
signal from the companded A-law or
µ–law
code,
a low-pass filter which corrects for the sin x/x re-
sponse of the decoder output and rejects signals
above 3400 Hz and is followed by a single-ended
power amplifier capable of driving low impedance
loads. The devices require 1.536 MHz, 1.544
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SO16 (Wide)
ORDERING NUMBERS:
ETC5057D
ETC5054D
PLCC20
ORDERING NUMBERS:
ETC5057FN
ETC5054FN
MHz, or 2.048 MHz transmit and receive master
clocks, which may be asynchronous, transmit and
receive bit clocks which may vary from 64 kHz to
2.048 MHz, and transmit and receive frame sync
pulses. The timing of the frame sync pulses and
PCM data is compatible with both industry stand-
ard formats.
1/18
March 2000
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
ETC5054 - ETC5057
PIN CONNECTIONS
(Top view)
DIP and SO
PLCC
BLOCK DIAGRAM
O
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2/18
ETC5054 - ETC5057
PIN DESCRIPTION
Name
V
BB
GNDA
VF
R
O
V
CC
FS
R
Pin
Type
*
S
GND
O
S
I
N°
N°
DIP PLCC
and
SO (**)
1
2
3
4
5
1
2
3
5
6
Function
Negative
Power Supply
Analog Ground
Receive Filter
Output
Positive Power
Supply
Receive Frame
Sync Pulse
Receive Data
Input
Shift-in Clock
V
BB
= – 5 V
±
5 %.
All signals are referenced to this pin.
Analog Output of the Receive Filter
V
CC
= + 5 V
±
5 %.
Enables BCLK
R
to shift PCM data into D
R
. FS
R
is an
8kHz pulse train. See figures 1, 2 and 3 for timing
details.
PCM data is shifted into D
R
following the FS
R
leading
edge.
Shifts data into D
R
after the FS
R
leading edge. May
vary from 64 kHz to 2.048 MHz. Alternatively, may be
a logic input which selects either 1.536 MHz/1.544
MHz or 2.048 MHz for master clock in synchronous
mode and BCLK
X
is used for both transmit and receive
directions (see table 1). This input has an internal pull-
up.
Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be
but should be
asynchronous with MCLK
X
,
synchronous with MCLK
X
for best performance. When
MCLK
R
is connected continuously low, MCLK
X
is
selected for all internal timing. When MCLK
R
is
connected continuously high, the device is powered
down.
Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLK
R
.
Description
D
R
BCLK
R
/CLKSEL
I
I
6
7
7
8
MCLK
R
/PDN
I
8
9
Receive Master Clock
MCLK
X
BCLK
X
D
X
FS
X
I
I
9
10
11
12
12
14
15
16
Transmit Master Clock
Shift-out Clock
Transmit
Data Output
O
I
TS
X
GS
X
VF
X
I
–
O
O
bs
O
VF
X
I
+
(*) I: Input, O: Output, S: Power Supply
(**) Pins 4,10,11 and 13 are not connected
TRI-STATE® is a trademark of National Semiconductor Corp.
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13
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Transmit Frame
Sync Pulse
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Shifts out the PCM data on DX. May vary from 64 kHz
to 2.048 MHz, but must be synchronous with MCLK
X
.
The TRI-STATE® PCM data output which is enabled
by FS
X
.
Transmit Time Slot
Gain Set
19
20
Inverting Amplifier
Input
Non-inverting Amplifier
Input
Enables BCLK
X
to shift out the PCM data on D
X
. FS
X
is
an 8 kHz pulse train. See figures 1, 2 and 3 for timing
details.
Open drain output which pulses low during the encoder
time slot. Recommended to be grounded if not used.
Analog output of the transmit input amplifier. Used to
set gain externally.
Inverting Input of the Transmit Input Amplifier.
Non-inverting Input of the Transmit Input Amplifier.
3/18
ETC5054 - ETC5057
FUNCTIONAL DESCRIPTION
POWER-UP
When power is first applied, power-on reset cir-
cuitry initializes the device and places it into
the power-down mode. All non-essential circuits
are deactivated and the D
X
and VF
R
O outputs are
put in high impedance states. To power-up the
device, a logical low level or clock must be ap-
plied to the MCLK
R
/PDN pin and FS
X
and/or FS
R
pulses must be present. Thus, 2 power-down
control modes are available. The first is to pull the
MCLK
R
/PDN pin high ; the alternative is to hold
both FS
X
and FS
R
inputs continuously low. The
device will power-down approximately 2 ms after
the last FS
X
or FS
R
pulse. Power-up will occur on
the first FS
X
or FS
R
pulse. The TRI-STATE PCM
data output, D
X
, will remain in the high impedance
state until the second FS
X
pulse.
SYNCHRONOUS OPERATION
For synchronous operation, the same master
clock and bit clock should be used for both the
transmit and receive directions. In this mode, a
clock must be applied to MCLK
X
and the
MCLK
R
/PDN pin can be used as a power-down
control. A low level on MCLK
R
/PDN powers up
the device and a high level powers down the de-
vice. In either case, MCLK
X
will be selected as
the master clock for both the transmit and receive
circuits. A bit clock must also be applied to BCLK
X
and the BCLK
R
/CKSEL can be used to select the
proper internal divider for a master clock of 1.536
MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz
operation, the device automatically compensates
for the 193rd clock pulse each frame. With a fixed
level on the BCLK
R
/CLKSEL pin, BCLK
X
will be
selected as the bit clock for both the transmit and
receive directions. Table 1 indicates the frequen-
cies of operation which can be selected, depend-
ing on the state of BCLK
R
/CLKSEL. In this syn-
chronous mode, the bit clock, BCLK
X
, may be
from 64 kHz to 2.048 MHz, but must be synchro-
nous with MCLK
X
.
Each FS
X
pulse begins the encoding cycle and
the PCM data from the previous encode cycle is
shifted out of the enabled D
X
output on the posi-
tive edge of BCLK
X
. After 8 bit clock periods, the
TRI-STATE D
X
output is returned to a high im-
pedance state. With and FS
R
pulse, PCM data is
latched via the D
R
input on the negative edge of
BCLK
X
(or BCLK
R
if running). FS
X
and FS
R
must
be synchronous with MCLK
X/R
.
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit
and receive clocks may be applied, MCLK
X
and
MCLK
R
must be 2.048 MHz for the ETC5057, or
1.536 MHz, 1.544 MHz for the ETC5054, and
need not be synchronous. For best transmission
performance, however, MCLK
R
should be syn-
chronous with MCLK
X
, which is easily achieved
by applying only static logic levels to the
MCLK
R
/PDN pin. This will automatically connect
MCLK
X
to all internal MCLK
R
functions (see pin
description). For 1.544 MHz operation, the device
automatically compensates for the 193rd clock
pulse each frame. FS
X
starts each encoding cycle
and must be synchronous with MCLK
X
and
BCLK
X
. FS
R
starts each decoding cycle and must
be synchronous with BCLK
R
. BCLK
R
must be a
clock, the logic levels shown in table 1 are not
valid in asynchronous mode. BCLK
X
and BCLK
R
may operate from 64 kHz to 2.048 MHz.
SHORT FRAME SYNC OPERATION
The device can utilize either a short frame sync
pulse or a long frame sync pulse. Upon power in-
itialization, the device assumes a short frame
mode. In this mode, both frame sync pulses, FS
X
and FS
R
, must be one bit clock period long, with
timing relationships specified in figure 2. With FS
X
high during a falling edge of BCLK
X
the next ris-
ing edge of BCLK
X
enables the D
X
TRI-STATE
output buffer, which will output the sign bit. The
following seven rising edges clock out the remain-
ing seven bits, and the next falling edge disables
the D
X
output. With FS
R
high during a falling edge
of BCLK
R
(BCLK
X
in synchronous mode), the
next falling edge of BCLK
R
latches in the sign bit.
The following seven falling edges latch in the
seven remaining bits. Both devices may utilize the
short frame sync pulse in synchronous or asyn-
chronous operating mode.
O
Table 1:
Selection of Master Clock Frequencies.
BCLK
R
/CLKSEL
Clocked
0
1 (or open circuit)
Master Clock Frequency
Selected
ETC5057
ETC5054
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
1.536 MHz or
1.544 MHz
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LONG FRAME SYNC OPERATION
To use the long frame mode, both the frame sync
pulses, FS
X
and FS
R
, must be three or more bit
clock periods long, with timing relationships speci-
fied in figure 3. Based on the transmit frame sync,
FS
X
, the device will sense whether short or long
frame sync pulses are being used. For 64 kHz op-
eration, the frame sync pulse must be kept low for
a minimum of 160 ns (see fig. 1). The D
X
TRI-
STATE output buffer is enabled with the rising
edge of FS
X
or the rising edge of BCLK
X
, which-
ever comes later, and the first bit clocked out is
the sign bit. The following seven BCLK
X
rising
4/18
ETC5054 - ETC5057
edges clock out the remaining seven bits. The D
X
output is disabled by the falling BCLK
X
edge fol-
lowing the eighth rising edge, or by FS
X
going
low, which-ever comes later. A rising edge on the
receive frame sync pulse, FS
R
, will cause the
PCM data at D
R
to be latched in on the next eight
falling edges of BCLK
R
(BCLK
X
in synchronous
mode). Both devices may utilize the long frame
sync pulse in synchronous or asynchronous
mode.
TRANSMIT SECTION
The transmit section input is an operational ampli-
fier with provision for gain adjustment using two
external resistors, see figure 6. The low noise and
wide bandwidth allow gains in excess of 20 dB
across the audio passband to be realized. The op
amp drives a unitygain filter consisting of RD ac-
tive pre-filter, followed by an eighth order
switched-capacitor bandpass filter clocked at 256
kHz. The output of this filter directly drives the en-
coder sample-and-hold circuit. The A/D is of com-
panding type according to A-law (ETC5057) or
µ–
law (ETC5054) coding conventions. A precision
voltage reference is trimmed in manufacturing to
provide an input overload (t
MAX
) of nominally 2.5V
peak (see table of transmission characteristics).
The FS
X
frame sync pulse controls the sampling
of the filter output, and then the successive-ap-
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
BB
V
IN
, V
OUT
T
oper
T
stg
Parameter
V
CC
to GNDA
V
BB
to GNDA
Voltage at any Analog Input or Output
Voltage at Any Digital Input or Output
proximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out
through D
X
at the next FS
X
pulse. The total en-
coding delay will be approximately 165
µs
(due to
the transmit filter) plus 125µs (due to encoding
delay), which totals 290µs. Any offset vol-tage
due to the filters or comparator is cancelled by
sign bit integration.
RECEIVE SECTION
The receive section consists of an expanding
DAC which drives a fifth order switched-capacitor
low pass filter clocked at 256 kHz. The decoder is
A-law (ETC5057) or
µ–law
(ETC5054) and the
5th order low pass filter corrects for the sin x/x at-
tenuation due to the 8 kHz sample and hold.
The filter is then followed by a 2nd order RC ac-
tive post-filter and power amplifier capable of driv-
ing a 600Ω load to a level of 7.2 dBm. The re-
ceive section is unity-gain. Upon the occurence of
FS
R
, the data at the D
R
input is clocked in on the
falling edge of the next eight BCLK
R
(BCLK
X
) pe-
riods. At the end of the decoder time slot, the de-
coding cycle begins, and 10µs later the decoder
DAC output is updated. The total decoder delay
is
∼
10µs (decoder update) plus 110µs (filter
delay) plus 62.5µs (1/2 frame), which gives ap-
proximately 180µs. A mute circuitry is a active
during 10ms when power up.
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
ELECTRICAL OPERATING CHARACTERISTICS
V
CC
= 5.0 V
±
5 %, V
BB
= – 5.0 V
±
5%GNDA = 0 V,
T
A
= 0
°C
to 70
°C;
Typical Characteristics Specified at V
CC
= 5.0 V, V
BB
= – 5.0 V, T
A
= 25
°C
; all signals
are referenced to GNDA.
O
Symbol
V
IL
V
IH
V
OL
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OH
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IL
I
IH
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Value
7
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Unit
V
V
V
V
°C
°C
°C
–7
V
CC
+ 0.3 to V
BB
– 0.3
V
CC
+ 0.3 to GNDA – 0.3
– 25 to + 125
– 65 to + 150
300
Parameter
Min.
2.2
Typ.
Input Low Voltage
Input High Voltage
Output Low Voltage
I
L
= 3.2mA
D
X
I
L
= 3.2mA, Open Drain
TS
X
Output High Voltage
I
H
= 3.2mA
D
X
Input Low Current (GNDA
≤
V
IN
≤
V
IL
, all digital inputs)
Input High Current (V
IH
≤
V
IN
≤
V
CC
) except BCLK
R
/BCLKSEL
Output Current in HIGH Impedance State (TRI-STATE)
(GNDA
≤
V
O
≤
V
CC
)
D
X
Max.
0.6
Unit
V
V
V
V
V
µA
µA
µA
5/18
0.4
0.4
2.4
–10
–10
–10
10
10
10
FPGA/CPLD
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