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Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
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by MC145484/D
MC145484
5 V PCM Codec-Filter
The MC145484 is a general purpose per channel PCM Codec–Filter with pin
DW SUFFIX
selectable Mu–Law or A–Law companding, and is offered in 20–pin SOG,
20
SOG PACKAGE
SSOP, and TSSOP packages. This device performs the voice digitization and
CASE 751D
1
reconstruction as well as the band limiting and smoothing required for PCM
systems. This device is designed to operate in both synchronous and
asynchronous applications and contains an on–chip precision reference
C.
SD SUFFIX
N
voltage.
SSOP
,I
This device has an input operational amplifier whose output is the input to the
R
20
CASE 940C
encoder section. The encoder section immediately low–pass filters the analog
TO
1
signal with an active R–C filter to eliminate very high frequency noise from being
UC
modulated down to the passband by the switched capacitor filter. From the
D
active R–C filter, the analog signal is converted to a differential signal. From this
N
DT SUFFIX
CO
point, all analog signal processing is done differentially. This allows processing
I
TSSOP
of an analog signal that is twice the amplitude allowed by a single–ended
CASE 948E
EM
20
S
design, which reduces the significance of noise to both the inverted and
E
non–inverted signal paths. Another advantage of this differential design is that
1
AL
noise injected via the power supplies is a common–mode signal that is
C
cancelled when the inverted and non–inverted signals
S
recombined. This
are
ORDERING INFORMATION
EE
dramatically improves the power supply rejection
R
ratio.
MC145484DW
SOG Package
After the differential converter, a differential
F
switched
Y
Hz before capacitor filter band–
MC145484SD
SSOP
passes the analog signal from 200 Hz to 3400
the signal is digitized
B
MC145484DT
TSSOP
by the differential compressing A/D converter.
ED
expands it using a differential D/A
The decoder accepts PCM data and
IV
H
converter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X
C
switched capacitor filter. The signal is then filtered
compensated by a differential
PIN ASSIGNMENT
AR
by an active R–C filter to eliminate the out–of–band energy of the switched
capacitor filter.
VAG
20
1
VAG Ref
The MC145484 PCM Codec–Filter has a high impedance VAG reference pin
TI+
19
2
RO-
which allows for decoupling of the internal circuitry that generates the
TI-
18
PI 3
mid–supply VAG reference voltage, to the VSS power supply ground. This
reduces clock noise on the analog circuitry when external analog signals are
TG
17
4
PO-
referenced to the power supply ground. This device is optimal for electronic
Mu/A
16
PO+
5
SLIC interfaces.
VSS
15
VDD 6
The MC145484 PCM Codec–Filter accepts a variety of clock formats,
including Short Frame Sync, Long Frame Sync, IDL, and GCI timing
FST
14
FSR 7
environments. This device also maintains compatibility with Motorola’s family
DT
13
DR 8
of Telecommunication products, including the MC14LC5472 and MC145572
BCLKT
12
BCLKR 9
U–Interface Transceivers, MC145474/75 and MC145574 S/T–Interface Trans-
c e i v e r s , M C 1 4 5 5 3 2 A D P C M Tr a n s c o d e r, M C 1 4 5 4 2 2 / 2 6 U D LT – 1 ,
11 MCLK
PDI 10
MC145421/25 UDLT–2, and MC3419/MC33120 SLICs.
The MC145484 PCM Codec–Filter utilizes CMOS due to its reliable
low–power performance and proven capability for complex analog/digital VLSI
functions.
•
•
•
•
•
•
•
•
•
Single 5 V Power Supply
Typical Power Dissipation of 15 mW, Power–Down of 0.01 mW
Fully–Differential Analog Circuit Design for Lowest Noise
Transmit Band–Pass and Receive Low–Pass Filters On–Chip
Active R–C Pre–Filtering and Post–Filtering
Mu–Law and A–Law Companding by Pin Selection
On–Chip Precision Reference Voltage of 1.575 V for a – 0 dBm TLP @ 600
Ω
Push–Pull 300
Ω
Power Drivers with External Gain Adjust
MC14LC5480EVK is the Evaluation Kit for This Device
Freescale Semiconductor, Inc...
REV 2
3/98
TN98031100
©
Motorola, Inc. 1998
MOTOROLA
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MC145484
1
Freescale Semiconductor, Inc.
RECEIVE
SHIFT
RO -
DAC
FREQ
PI
REGISTER
DR
PO -
-
+
FSR
BCLKR
SHARED
DAC
Mu/A
PO +
VDD
VSS
VAG Ref
-1
SEQUENCE
VDD
R*
1.575 V
REF
1
R*
VSS
TG
TI -
TI +
-
+
Freescale Semiconductor, Inc...
VAG
HI
RC
A
DEVICE DESCRIPTION
Figure 1. MC145484 5 V PCM Codec–Filter Block Diagram
VE
which increment. When the chord bits increment, the step
bits double their voltage weighting. This results in an effec-
tive resolution of six bits (sign + chord + four step bits) across
a 42 dB dynamic range (seven chords above 0, by 6 dB per
chord).
In a sampling environment, Nyquist theory says that to
properly sample a continuous signal, it must be sampled at a
frequency higher than twice the signal’s highest frequency
component. Voice contains spectral energy above 3 kHz, but
its absence is not detrimental to intelligibility. To reduce the
digital data rate, which is proportional to the sampling rate, a
sample rate of 8 kHz was adopted, consistent with a band-
width of 3 kHz. This sampling requires a low–pass filter to
limit the high frequency energy above 3 kHz from distorting
the in–band signal. The telephone line is also subject to
50/60 Hz power line coupling, which must be attenuated
from the signal by a high–pass filter before the analog–to–
digital converter.
The digital–to–analog conversion process reconstructs a
staircase version of the desired in–band signal, which has
spectral images of the in–band signal modulated about the
sample frequency and its harmonics. These spectral images
are called aliasing components, which need to be attenuated
to obtain the desired signal. The low–pass filter used to at-
tenuate these aliasing components is typically called a re-
construction or smoothing filter.
The MC145484 PCM Codec–Filter has the codec, both
presampling and reconstruction filters, and a precision volt-
age reference on–chip.
D
BY
EE
FR
FREQ
LE
CA
S
S
CO
I
M
E
ADC
,I
OR
CT
DU
N
CONTROL
AND
C.
N
PDI
MCLK
BCLKT
FST
TRANSMIT
SHIFT
REGISTER
DT
A PCM Codec–Filter is used for digitizing and reconstruct-
ing the human voice. These devices are used primarily for
the telephone network to facilitate voice switching and trans-
mission. Once the voice is digitized, it may be switched by
digital switching methods or transmitted long distance (T1,
microwave, satellites, etc.) without degradation. The name
codec is an acronym from ‘‘COder’’ for the analog–to–digital
converter (ADC) used to digitize voice, and ‘‘DECoder’’ for
the digital–to–analog converter (DAC) used for reconstruct-
ing voice. A codec is a single device that does both the ADC
and DAC conversions.
To digitize intelligible voice requires a signal–to–distortion
ratio of about 30 dB over a dynamic range of about 40 dB.
This may be accomplished with a linear 13–bit ADC and
DAC, but will far exceed the required signal–to–distortion
ratio at larger amplitudes than 40 dB below the peak ampli-
tude. This excess performance is at the expense of data per
sample. Two methods of data reduction are implemented by
compressing the 13–bit linear scheme to companded
pseudo–logarithmic 8–bit schemes. The two companding
schemes are: Mu–255 Law, primarily in North America and
Japan; and A–Law, primarily used in Europe. These com-
panding schemes are accepted world wide. These compand-
ing schemes follow a segmented or ‘‘piecewise–linear’’ curve
formatted as sign bit, three chord bits, and four step bits. For
a given chord, all sixteen of the steps have the same voltage
weighting. As the voltage of the analog input increases, the
four step bits increment and carry to the three chord bits
MC145484
2
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Freescale Semiconductor, Inc.
PIN DESCRIPTIONS
POWER SUPPLY
VDD
Positive Power Supply (Pin 6)
This is the most positive power supply and is typically con-
nected to + 5 V. This pin should be decoupled to VSS with a
0.1
µF
ceramic capacitor.
VSS
Negative Power Supply (Pin 15)
This is the most negative power supply and is typically
connected to 0 V.
VAG
Analog Ground Output (Pin 20)
become high impedance and the VAG Ref pin is pulled to the
VDD power supply with a non–linear, high–impedance circuit.
The device will operate normally when a logic 1 is applied to
this pin. The device goes through a power–up sequence
when this pin is taken to a logic 1 state, which prevents the
DT PCM output from going low impedance for at least two
FST cycles. The VAG and VAG Ref circuits and the signal pro-
cessing filters must settle out before the DT PCM output or
the RO– receive analog output will represent a valid analog
signal.
ANALOG INTERFACE
TI+
Transmit Analog Input (Non–Inverting) (Pin 19)
C.
This is the non–inverting input of the transmit input gain
,I
setting operational amplifier. This pin accommodates a differ-
OR
for the input gain setting op
ential to single–ended
T
This output pin provides a mid–supply analog ground. This
C
circuit
amp. This allows input signals that are referenced to the V SS
pin should be decoupled to VSS with a 0.01
µF
ceramic
DU
pin to be level shifted to the VAG pin with minimum noise.
capacitor. All analog signal processing within this device is
N
This pin
CO
be connected to the VAG pin for an inverting
may
referenced to this pin. If the audio signals to be processed
I
amplifier configuration if the input signal is already refer-
are referenced to V SS, then special precautions must be
M
enced to the VAG pin. The common mode range of the TI+
utilized to avoid noise between V SS and the VAG pin. Refer to
SE
TI– pins is from 1.2 V, to V minus 1.2 V. This is an FET
the applications information in this document for more in-
DD
LE
and input.
gate
formation. The VAG pin becomes high impedance when this
CA
The TI+ pin also serves as a digital input control for the
device is in the powered–down mode.
ES
transmit input multiplexer. Connecting the TI+ pin to VDD will
RE
VAG Ref
place this amplifier’s output (TG) into a high–impedance
F
Analog Ground Reference Bypass (Pin 1)
state, and selects the TG pin to serve as a high–impedance
BY
on–chip cir-
input to the transmit filter. Connecting the TI+ pin to VSS will
This pin is used to capacitively bypass the
D
also place this amplifier’s output (TG) into a high–impedance
cuitry that generates the mid–supply
E
the
IV
voltage forwith VAG out-
state, and selects the TI– pin to serve as a high–impedance
put pin. This pin should be bypassed to VSS
a 0.1
µF
H
input to the transmit filter.
ceramic capacitor using short, low inductance traces. The
RC
A
VAG Ref pin is only used for generating the reference voltage
TI–
for the VAG pin. Nothing is to be connected to this pin in addi-
Transmit Analog Input (Inverting) (Pin 18)
tion to the bypass capacitor. All analog signal processing
within this device is referenced to the VAG pin. If the audio
This is the inverting input of the transmit gain setting op-
signals to be processed are referenced to VSS, then special
erational amplifier. Gain setting resistors are usually con-
precautions must be utilized to avoid noise between VSS and
nected from this pin to TG and from this pin to the analog
the VAG pin. Refer to the applications information in this
signal source. The common mode range of the TI+ and TI–
document for more information. When this device is in the
pins is from 1.2 V to VDD – 1.2 V. This is an FET gate input.
powered–down mode, the VAG Ref pin is pulled to the VDD
The TI– pin also serves as one of the transmit input multi-
power supply with a non–linear, high–impedance circuit.
plexer pins when the TI+ pin is connected to VSS. When TI+
is connected to VDD, this pin is ignored. See the pin descrip-
CONTROL
tions for the TI+ and the TG pins for more information.
Mu/A
TG
Mu/A Law Select (Pin 16)
Transmit Gain (Pin 17)
This pin controls the compression for the encoder and the
expansion for the decoder. Mu–Law companding is selected
This is the output of the transmit gain setting operational
when this pin is connected to VDD and A–Law companding is
amplifier and the input to the transmit band–pass filter. This
selected when this pin is connected to VSS.
op amp is capable of driving a 2 kΩ load. Connecting the TI+
pin to VDD will place the TG pin into a high–impedance state,
PDI
and selects the TG pin to serve as a high–impedance input to
Power–Down Input (Pin 10)
the transmit filter. All signals at this pin are referenced to the
This pin puts the device into a low power dissipation mode
VAG pin. When TI+ is connected to VSS, this pin is ignored.
when a logic 0 is applied. When this device is powered down,
See the pin descriptions for the TI+ and TI– pins for more in-
all of the clocks are gated off and all bias currents are turned
formation. This pin is high impedance when the device is in
off, which causes RO–, PO–, PO+, TG, VAG, and DT to
the powered–down mode.
N
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3
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RO–
Receive Analog Output (Inverting) (Pin 2)
This is the inverting output of the receive smoothing filter
from the digital–to–analog converter. This output is capable
of driving a 2 kΩ load to 1.575 V peak referenced to the VAG
pin. If the device is operated half–channel with the FST pin
clocking and FSR pin held low, the receive filter input will be
conencted to the VAG voltage. This minimizes transients at
the RO– pin when full–channel operation is resumed by
clocking the FSR pin. This pin is high impedance when the
device is in the powered–down mode.
PI
Power Amplifier Input (Pin 3)
This is the inverting input to the PO– amplifier. The non–
inverting input to the PO– amplifier is internally tied to the
VAG pin. The PI and PO– pins are used with external resis-
tors in an inverting op amp gain circuit to set the gain of the
PO+ and PO– push–pull power amplifier outputs. Connect-
ing PI to VDD will power down the power driver amplifiers and
the PO+ and PO– outputs will be high impedance.
PO–
Power Amplifier Output (Inverting) (Pin 4)
this pin to the clock at FST (8 kHz) and will automatically
accept 256, 512, 1536, 1544, 2048, 2560, or 4096 kHz. For
MCLK frequencies of 256 and 512 kHz, MCLK must be syn-
chronous and approximately rising edge aligned to FST. For
optimum performance at frequencies of 1.536 MHz and
higher, MCLK should be synchronous and approximately ris-
ing edge aligned to the rising edge of FST. In many ap-
plications, MCLK may be tied to the BCLKT pin.
FST
Frame Sync, Transmit (Pin 14)
This pin accepts an 8 kHz clock that synchronizes the out-
put of the serial PCM data at the DT pin. This input is com-
patible with various standards including IDL, Long Frame
C.
Sync, Short Frame Sync, and GCI formats. If both FST and
N
,
8
I
kHz frames, the device will
FSR are held low for several
OR
power down.
Freescale Semiconductor, Inc...
This is the inverting power amplifier output, which is used
EE
to provide a feedback signal to the PI pin to set
R
gain of
F
the
the push–pull power amplifier outputs. This
Y
is capable of
pin
B
PO– outputs are
driving a 300
Ω
load to PO+. The PO+ and
differential (push–pull) and capable of driving a 300
Ω
load to
ED
IV
3.15 V peak, which is 6.3 V peak–to–peak. The bias voltage
H
and signal reference of this
C
output is the VAG pin. The VAG
pin cannot source or sink as much current as this pin, and
AR
therefore low impedance loads must be between PO+ and
PO–. The PO+ and PO– differential drivers are also capable
of driving a 100
Ω
resistive load or a 100 nF Piezoelectric
transducer in series with a 20
Ω
resister with a small increase
in distortion. These drivers may be used to drive resistive
loads of
≥
32
Ω
when the gain of PO– is set to 1/4 or less.
Connecting PI to VDD will power down the power driver am-
plifiers and the PO+ and PO– outputs will be high imped-
ance. This pin is also high impedance when the device is
powered down by the PDI pin.
PO+
Power Amplifier Output (Non–Inverting) (Pin 5)
This is the non–inverting power amplifier output, which is
an inverted version of the signal at PO–. This pin is capable
of driving a 300
Ω
load to PO–. Connecting PI to VDD will
power down the power driver amplifiers and the PO+ and
PO– outputs will be high impedance. This pin is also high im-
pedance when the device is powered down by the PDI pin.
See PI and PO– for more information.
DIGITAL INTERFACE
MCLK
Master Clock (Pin 11)
clock fre-
E
the receive PCMtodata. This pin can accept any bit and Short
from
AL
quency Sync 64 4096 kHz for Long Frame Sync
Frame
timing. This pin can accept clock frequencies
SC
CT
BCLKT
DU
(Pin 12)
Bit Clock, Transmit
ON
This pin controls the transfer rate of transmit PCM data. In
IC
M
and GCI modes it also controls the transfer rate of
the
E
IDL
S
from 256 kHz to 4.096 MHz in IDL mode, and from 512 kHz
to 6.176 MHz for GCI timing mode.
DT
Data, Transmit (Pin 13)
This pin is controlled by FST and BCLKT and is high im-
pedance except when outputting PCM data. When operating
in the IDL or GCI mode, data is output in either the B1 or B2
channel as selected by FSR. This pin is high impedance
when the device is in the powered down mode.
FSR
Frame Sync, Receive (Pin 7)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts an 8 kHz clock, which synchronizes
the input of the serial PCM data at the DR pin. FSR can be
asynchronous to FST in the Long Frame Sync or Short
Frame Sync modes. When an ISDN mode (IDL or GCI) has
been selected with BCLKR, this pin selects either B1 (logic 0)
or B2 (logic 1) as the active data channel.
BCLKR
Bit Clock, Receive (Pin 9)
When used in the Long Frame Sync or Short Frame Sync
mode, this pin accepts any bit clock frequency from 64 to
4096 kHz. When this pin is held at a logic 1, FST, BCLKT, DT,
and DR become IDL Interface compatible. When this pin is
held at a logic 0, FST, BCLKT, DT, and DR become GCI Inter-
face compatible.
DR
Data, Receive (Pin 8)
This pin is the PCM data input, and when in a Long Frame
Sync or Short Frame Sync mode is controlled by FSR and
BCLKR. When in the IDL or GCI mode, this data transfer is
controlled by FST and BCLKT. FSR and BCLKR select the
B channel and ISDN mode, respectively.
This is the master clock input pin. The clock signal applied
to this pin is used to generate the internal 256 kHz clock and
sequencing signals for the switched–capacitor filters, ADC,
and DAC. The internal prescaler logic compares the clock on
MC145484
4
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FUNCTIONAL DESCRIPTION
ANALOG INTERFACE AND SIGNAL PATH
tors. The PO+ amplifier has a gain of minus one, and is in-
ternally connected to the PO– output. This complete power
amplifier circuit is a differential (push–pull) amplifier with ad-
justable gain that is capable of driving a 300
Ω
load to
+ 12 dBm. The power amplifier may be powered down inde-
pendently of the rest of the chip by connecting the PI pin to
VDD.
The transmit portion of this device includes a low–noise,
three–terminal op amp capable of driving a 2 kΩ load. This
op amp has inputs of TI+ (Pin 19) and TI– (Pin 18) and its
output is TG (Pin 17). This op amp is intended to be confi-
gured in an inverting gain circuit. The analog signal may be
POWER–DOWN
applied directly to the TG pin if this transmit op amp is inde-
pendently powered down by connecting the TI+ input to the
There are two methods of putting this device into a low
VDD power supply. The TG pin becomes high impedance
power consumption mode, which makes the device nonfunc-
when the transmit op amp is powered down. The TG pin is
tional and consumes virtually no power. PDI is the power–
internally connected to a 3–pole anti–aliasing pre–filter. This
down input pin which, when taken low, powers down the
pre–filter incorporates a 2–pole Butterworth active low–pass
device. Another way to power the device down is to hold both
C.
filter, followed by a single passive pole. This pre–filter is fol-
the FST and FSR pins low while
N
BCLKT and MCLK pins
I
the
,
powered down, the V , TG,
lowed by a single–ended to differential converter that is
are clocked. When the chip
R
is
AG
O
outputs are high impedance and
clocked at 512 kHz. All subsequent analog processing uti-
RO–, PO+, PO–, and
T
DT
lizes fully–differential circuitry. The next section is a fully–
the VAG Ref pin is pulled to the VDD power supply with a non–
UC
differential, 5–pole switched–capacitor low–pass filter with
linear, high–impedance circuit. To return the chip to the pow-
ND
be high and the FST frame sync pulse
a 3.4 kHz frequency cutoff. After this filter is a 3–pole
er–up state, PDI must
CO
switched–capacitor high–pass filter having a cutoff fre-
I
must be present while the BCLKT and MCLK pins are
M
The DT output will remain in a high–impedance
quency of about 200 Hz. This high–pass stage has a trans-
clocked.
SE
for at least two 8 kHz FST pulses after power–up.
mission zero at dc that eliminates any dc coming from the
state
analog input or from accumulated op amp offsets in the pre-
LE
ceding filter stages. The last stage of the high–pass filter
CA
is
MASTER CLOCK
S
an autozeroed sample and hold amplifier.
E
Since this codec–filter design has a single DAC architec-
One bandgap voltage reference generator and
RE
digital–to–
ture, the MCLK pin is used as the master clock for all analog
F
analog converter (DAC) are shared by the transmit and re-
Y
signal processing including analog–to–digital conversion,
ceive sections. The autozeroed, switched–capacitor
B
digital–to–analog conversion, and for transmit and receive fil-
bandgap reference generates precise
D
negative
E
positive and tempera-
tering functions of this device. The clock frequency applied to
reference voltages that are virtually independent of
IV
the MCLK pin may be 256 kHz, 512 kHz, 1.536 MHz,
ture and power supply voltage. A binary–weighted capacitor
CH
the companding structure,
1.544 MHz, 2.048 MHz, 2.56 MHz, or 4.096 MHz. This de-
R
array (CDAC) forms the chords of
A
vice has a prescaler that automatically determines the proper
while a resistor string (RDAC) implements the linear steps
divide ratio to use for the MCLK input, which achieves the re-
within each chord. The encode process uses the DAC, the
quired 256 kHz internal sequencing clock. The clocking re-
voltage reference, and a frame–by–frame autozeroed
quirements of the MCLK input are independent of the PCM
comparator to implement a successive–approximation con-
data transfer mode (i.e., Long Frame Sync, Short Frame
version algorithm. All of the analog circuitry involved in the
Sync, IDL mode, or GCI mode).
data conversion (the voltage reference, RDAC, CDAC, and
comparator) are implemented with a differential architecture.
DIGITAL I/O
The receive section includes the DAC described above, a
The MC145484 is pin selectable for Mu–Law or A–Law.
sample and hold amplifier, a 5–pole, 3400 Hz switched ca-
Table 1 shows the 8–bit data word format for positive and
pacitor low–pass filter with sinX/X correction, and a 2–pole
negative zero and full scale for both companding schemes.
active smoothing filter to reduce the spectral components of
Table 2 shows the series of eight PCM words for both Mu–
the switched capacitor filter. The output of the smoothing fil-
Law and A–Law that correspond to a digital milliwatt. The
ter is buffered by an amplifier, which is output at the RO– pin.
digital mW is the 1 kHz calibration signal reconstructed by
This output is capable of driving a 2 kΩ load to the VAG pin.
the DAC that defines the absolute gain or 0 dBm0 Transmis-
The MC145484 also has a pair of power amplifiers that are
sion Level Point (TLP) of the DAC. The timing for the PCM
connected in a push–pull configuration. The PI pin is the in-
data transfer is independent of the companding scheme se-
verting input to the PO– power amplifier. The non–inverting
lected. Refer to Figure 2 for a summary and comparison of
input is internally tied to the VAG pin. This allows this amplifier
the four PCM data interface modes of this device.
to be used in an inverting gain circuit with two external resis-
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MC145484
5
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