Errata Sheet for Arria II GX Devices
ES-01025-3.7
Errata Sheet
This errata sheet provides updated information about known device issues affecting
Arria
®
II GX devices.
Table 1
lists the specific issues and which Arria II GX devices are affected.
Table 1. Issues for Arria II GX Devices (Part 1 of 2)
Issue
“EDCRC False Error”
The error detection CRC (SEU detection) feature may falsely
assert the
CRC_ERROR
signal when no SEU event has occurred.
“PLL phasedone Signal Stuck at Low”
In some cases, the Arria II GX phase-locked loop (PLL) blocks
exhibit the
phasedone
signal stuck at low during the PLL
dynamic phase shift.
“Transmitter PLL Lock (pll_locked) Status Signal”
The transmitter PLL lock status signal (pll_locked) does not
de-assert when the
pll_powerdown
signal is asserted in
configurations that use the reference clock pre-divider of 2, 4,
or 8.
“Dynamic Reconfiguration Issue Between PCIe Mode and Any
Other Transceiver Mode”
The transceiver may not be initialized correctly if your application
uses dynamic reconfiguration to change the transceiver channel
between PCI Express
®
(PCIe
®
) mode and any other transceiver
mode.
“Quartus II Software Incorrect Setting for the Transceiver CDR in
All Modes Except PCIe Mode”
The Quartus II software incorrectly sets the CDR unit when the
transceiver channel is configured in any mode except PCIe mode
and you configure the CDR to automatic lock mode.
External Memory Interface DLL Frequency Range Update
New f
MIN
for the DLL frequency range and a new frequency
mode 6.
Quartus II Mapping Issue with PCIe Interfaces Using the Hard IP
Block
The Quartus II software incorrectly maps the PCIe interfaces
when using the hard IP block.
®
Affected Devices
All production devices
Planned Fix
—
All production devices
Quartus II software version
12.0 and later.
All production devices
No plan to fix silicon. For a
soft-fix solution, refer to
“Transmitter PLL Lock
(pll_locked) Status Signal”.
No plan to fix silicon. Apply
the reset workaround in
“Dynamic Reconfiguration
Issue Between PCIe Mode
and Any Other Transceiver
Mode”.
Quartus II software version
10.1 and later.
Patches are available for the
Quartus II software
versions 9.1SP2 and
10.0SP1.
Software fix
All Arria II GX
(ES and Production)
Devices
All Arria II GX
(ES and Production)
Devices
All Arria II GX
(ES and Production)
devices
All Arria II GX
(ES and production)
devices
Software fix
101 Innovation Drive
San Jose, CA 95134
www.altera.com
© 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS,
QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark
Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their
respective holders as described at
www.altera.com/common/legal.html.
Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use
of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are
advised to obtain the latest version of device specifications before relying on any published information and before placing orders
for products or services.
ISO
9001:2008
Registered
April 2013
Altera Corporation
Subscribe
Page 2
EDCRC False Error
Table 1. Issues for Arria II GX Devices (Part 2 of 2)
Issue
XAUI State Machine Failure—Channel 0 Shifted by One Cycle
Channel 0 data is shifted by one cycle with respect to Channels 1,
2, and 3.
High I/O Pin Leakage Current
All I/O pins have higher leakage than the published
Device
Datasheet for Arria II Devices
chapter, version 1.2 specifications.
Error Detection CRC Feature
When enabled, the Error Detection CRC feature may cause the
MLAB RAM blocks to operate incorrectly.
M9K RAM Block Lock-Up
The M9K RAM blocks may lock up due to a glitchy non-PLL
clock.
Automatic Clock Switchover
The automatic clock switchover feature may not operate correctly.
Remote System Upgrade
The remote system upgrade feature fails when loading an invalid
configuration image.
EP2AGX125 ES
EP2AGX125 ES
EP2AGX125 ES
Production devices
EP2AGX125 ES
Production devices
Affected Devices
Planned Fix
EP2AGX125 production
devices
EP2AGX125 production
devices
None
EP2AGX125 ES
All Arria II GX
(ES and Production)
Devices
Software fix
EDCRC False Error
The error detection cyclic redundancy check (CRC) (single event upset [SEU]
detection) feature may falsely assert the
CRC_ERROR
signal when no SEU event has
occurred. This happens because the configuration RAM is incorrectly read for the
EDCRC checks. In this scenario, the configuration RAM data and the functionality of
the device are not affected.
■
■
If EDCRC is not critical to your system, turn it off.
If EDCRC is required, insert a soft IP in your design.
f
For more support and to request the soft IP, file a service request using
mySupport.
PLL phasedone Signal Stuck at Low
In some cases, the Arria II GX PLL blocks exhibit the
phasedone
signal stuck at low
during the PLL dynamic phase shift. When the PLL
phasedone
signal is stuck at low,
the intended phase shift does not happen. You can recover from the PLL
phasedone
signal being stuck at low by resetting the PLL or by restarting the phase shift
operation by asserting the
phasestep
signal.
Solution
To resolve the PLL
phasedone
signal stuck at low issue, the Altera
®
PLL megafunction
is enhanced to automatically restart the phase shift operation internally in the Altera
PLL megafunction whenever the PLL
phasedone
signal is stuck at low. Restarting the
phase shift operation compensates for the missing phase shift operation and also
recovers the
phasedone
signal.
April 2013
Altera Corporation
Errata Sheet for Arria II GX Devices
Transmitter PLL Lock (pll_locked) Status Signal
Page 3
This Altera PLL megafunction solution will be implemented in the Quartus II
software version 12.0 and later. Altera recommends upgrading to the latest Quartus II
software, regenerating the PLL megafunction, and recompiling your design.
Additionally, software patches are available for the Quartus II software versions 9.1
SP2 and 10.1 SP1 to upgrade the PLL megafunction with the solution. To download
and install the Quartus II software patch, refer to the
PLL Phasedone Stuck at Low
Solution.
If you need additional support, file a service request using
mySupport.
Transmitter PLL Lock (pll_locked) Status Signal
The transmitter phase-locked loop (PLL) lock status signal (pll_locked) does not
de-assert when the
pll_powerdown
signal is asserted in configurations that use the
reference clock pre-divider of 2, 4, or 8.
Figure 1
shows the reference clock pre-divider
inside transmitter PLLs. This issue impacts the
pll_locked
status signal in the clock
multiplier unit (CMU) PLL.
Figure 1. Reference Clock Pre-Dividers in Transmitter PLLs
CMU PLL
Lock
Detect
pll_locked
/M
Input Reference
Clock
/1, /2, /4, /8
PFD
Charge Pump
+
Loop Filter
VCO
/L
CMU0
High-Speed
Clock
Reference Clock
Pre-Divider
f
Designs that implement the recommended transceiver reset sequence described in the
Reset Control and Power Down in Arria II Devices
chapter in volume 2 of the
Arria II
Device Handbook
could potentially see a link failure after coming out of reset.
Errata Sheet for Arria II GX Devices
April 2013
Altera Corporation
Page 4
Transmitter PLL Lock (pll_locked) Status Signal
You can determine if the Transmitter PLL in your design uses a reference clock
pre-divider of 2, 4, or 8 by referring to the Quartus II software Compilation Report.
Figure 2
shows an example of the “GXB Transmitter PLL” report, which you find in
the “Resources Section” under “Fitter” in the Compilation Report. If the value in the
“Divide By” column reads 2, 4, or 8, your design is impacted by the
pll_locked
status
signal issue.
Figure 2. Determining Reference Clock Pre-Divider Value in the Compilation Report
Workaround
If the
pll_locked
issue impacts your design, instantiate and connect the
pll_locked_soft_logic
module, as shown in
Figure 3.
You must use the
pll_locked_to_corelogic
output from this module in the transceiver reset logic and
any user logic that relies on the transmitter PLL lock status signal.
Figure 3. Instantiating and Connecting the pll_locked_soft_logic Module
serdes_io
top_cal_blk_clk
top_pll_inclk
xcvr_reset_logic
xcvr_async_reset
system_clk
xcvr_async_reset
clk
tx_digitalreset
pll_locked
inst3
pll_locked_soft_logic
clk
reset
pll_locked_from_altgx
inst2
pll_locked_to_corelogic
tx_digitalreset[0..0]
inst
pll_powerdown
tx_datain[39..0]
cal_blk_clk
pll_inclk
pll_powerdown[0..0]
tx_datain[39..0]
pll_locked[0..0]
tx_clkout[0..0]
tx_dataout[0..0]
top_tx_dataout
f
Click
pll_locked_soft_logic
to obtain the module.
April 2013
Altera Corporation
Errata Sheet for Arria II GX Devices
Dynamic Reconfiguration Issue Between PCIe Mode and Any Other Transceiver Mode
Page 5
Use the calibration block clock (cal_blk_clk) for the
pll_locked_soft_logic
module.
The
cal_blk_clk
frequency specification ranges from 10 MHz to 125 MHz.
Depending on your
cal_blk_clk
frequency, set the parameter
p_delay_counter
in the
pll_locked_soft_logic
so that the delay is equal to 100
s
(worst-case transmitter
PLL lock time).
Dynamic Reconfiguration Issue Between PCIe Mode and Any Other
Transceiver Mode
If your application uses dynamic reconfiguration to change the transceiver channel
between PCIe mode and any other transceiver mode, the transceiver may not be
initialized correctly, resulting in receiver bit errors.
1
This problem only affects dynamic reconfiguration between PCIe mode and any other
transceiver mode. Dynamic reconfiguration between any transceiver modes other
than PCIe mode is not affected.
Workaround
f
If you see bit errors, apply the reset sequence described in the
Reset Sequence
Solution.
f
If you need additional support, file a service request at Altera's
mysupport.
Quartus II Software Incorrect Setting for the Transceiver CDR in All
Modes Except PCIe Mode
The Quartus II software versions up to and including 10.0 SP1 incorrectly set the clock
and data recovery (CDR) unit when the transceiver channel is configured in any mode
except PCIe mode and the CDR is configured in automatic lock mode.
When there are no data transitions on the transceiver data inputs for an extended
period of time (in the ms range), the CDR may keep the
rx_freqlocked
signal
asserted. The CDR does not return to the lock-to-reference state and incorrect data
may be recovered.
1
The transceiver channels configured in PCIe mode are NOT affected by this issue.
Solution
This issue is fixed in the Quartus II software versions 10.1 and later. Altera
recommends upgrading to the latest Quartus II software and recompiling your
design. For complete details of the solution, refer to the
Transceiver CDR Solution.
Additionally, software patches are available for the Quartus II software versions
9.1 SP2 and 10.0 SP1.
f
To download and install the patch, refer to the
Transceiver CDR Solution.
Errata Sheet for Arria II GX Devices
April 2013
Altera Corporation
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