IDT72T6480L7-5BB,IDT72T6480L7-5BB pdf中文资料,IDT72T6480L7-5BB引脚图,IDT72T6480L7-5BB电路-Datasheet-电子工程世界

Datasheet> 器件分类 > 半导体> 其他集成电路（IC）> IDT72T6480L7-5BB

文档预览

IDT72T6480L7-5BB: 产品描述IC flow-ctrl 48bit 7-5ns 324-bga; 产品类别半导体其他集成电路（IC）; 文件大小388KB，共51页; 制造商IDT(艾迪悌); 官网地址http://www.idt.com/

下载文档选型对比全文预览

IDT72T6480L7-5BB概述

IC flow-ctrl 48bit 7-5ns 324-bga

文档预览

下载PDF文档

全文
预览

2.5V SEQUENTIAL FLOW-CONTROL DEVICE

48 BIT WIDE CONFIGURATION

For use with 128Mb to 256Mb DDR SDRAM

IDT72T6480

FEATURES

•

Product to be used with single or multiple external DDR SDRAM

•

to provide significant storage capability of up to 1Gb density

133MHz operation (7.5ns read/write cycle time)

User selectable input and output port bus-sizing

- x48in to x48out

- x48in to x24out

- x48in to x12out

- x24in to x48out

- x24in to x24out

- x24in to x12out

- x12in to x48out

- x12in to x24out

- x12in to x12out

For other bus configurations see IDT72T6360 (x9, x18, or x36)

2.5V-LVTTL or 3.3V-LVTTL configured ports

Independent and simultaneous read and write access

User selectable synchronous/asynchronous read and write

port timing

•

IDT Standard mode or FWFT mode of operation

•

Empty and full flags for monitoring memory status

•

Programmable Almost-Empty and Almost-Full flags, each flag

can default to one of four preselected offsets or serially

programmed to a specific value

•

Selectable synchronous/asynchronous timing modes for

Almost-Empty and Almost-Full flags

•

Master Reset clears all data and settings

•

Partial Reset clears data, but retains programmable settings

•

Depth expandable with multiple devices for densities greater

than 1Gb

•

Width expandable with multiple devices for bus widths greater

than 36 bits

•

JTAG functionality (Boundary Scan)

•

Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm

•

HIGH performance 0.18µm CMOS technology

•

Industrial temperature range (-40°C to +85°C) is available

•

Supports industry standard DDR specifications, including

Samsung, Micron, and Infineon memories

•

FUNCTIONAL BLOCK DIAGRAM

FWFT

I/O Bus

Configuration

36-bits

FF/IR

PAF

EF/OR

PAE

Flag

Logic

Reset

Logic

FSEL[1:0]

IDT72T6480

Sequential Flow Control Device

MRS

PRS

IOSEL

BM[3:0]

36-bits

x48, x24, or x12

Output Register

Input Register

x48, x24, or x12

36-bits

WEN

WCLK/WR

WCS

ASYW

Read

Control Logic

Write

Control Logic

REN

RCLK/RD

RCS

ASYR

DDR SDRAM

Control Logic

MCLK

CK DQS

WE CAS RAS

Addr

JTAG

Control

(Boundary Scan)

TDO/SO

TCK/SCLK

TMS

TDI/SI

Data

6358 drw01

High Density DDR SDRAM

x16, x32, x36, or x64

128Mb to 256Mb

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

FEBRUARY 2009

DSC-6358/6

IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE

x12, x24, x48 BIT WIDE CONFIGURATION

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

Table of Contents

Features ......................................................................................................................................................................................................................... 1

Description ...................................................................................................................................................................................................................... 4

Pin Configuration ............................................................................................................................................................................................................. 6

Pin Descriptions .......................................................................................................................................................................................................... 7-10

- Read Port Interface ........................................................................................................................................................................................... 7

- Write Port Interface ............................................................................................................................................................................................ 7

- Memory Interface .............................................................................................................................................................................................. 8

- Control and Feature Interface ............................................................................................................................................................................ 8

- Power and Ground Signals ............................................................................................................................................................................. 10

- Pin Number Location Table .............................................................................................................................................................................. 10

Detailed Descriptions ..................................................................................................................................................................................................... 11

Functional Descriptions .................................................................................................................................................................................................. 22

Signal Descriptions ........................................................................................................................................................................................................ 23

Device Characteristics ................................................................................................................................................................................................... 27

AC Test Conditions ........................................................................................................................................................................................................ 29

AC Electrical Characteristics ........................................................................................................................................................................................... 30

JTAG Timing Specifications ............................................................................................................................................................................................ 45

Depth Expansion Configuration ..................................................................................................................................................................................... 49

Width Expansion Configuration ...................................................................................................................................................................................... 50

Ordering Information ...................................................................................................................................................................................................... 51

List of Tables

Table 1 – DDR SDRAM Minimum Specifications ............................................................................................................................................................. 11

Table 2 – Supported Memory Vendors .......................................................................................................................................................................... 11

Table 3 – Total Possible External Memory Configurations ............................................................................................................................................... 12

Table 4 – SFC to DDR SDRAM interface Connections ................................................................................................................................................... 14

Table 5 – Total useable memory based on various configurations ................................................................................................................................... 18

Table 6 – IDT72T6480 Maximum Frequency Based on 166MHz DDR SDRAM ............................................................................................................ 19

Table 7 – IDT72T6480 Maximum Frequency Based on 133MHz DDR SDRAM ............................................................................................................ 19

Table 8 – MIC[2:0] Configurations .................................................................................................................................................................................. 20

Table 9 – Memory Configurations Settings ..................................................................................................................................................................... 21

Table 10 – Device configuration ..................................................................................................................................................................................... 22

Table 11– Default Programmable Flag Offsets ................................................................................................................................................................. 22

Table 12– Number of Bits Required for Offset Registers .................................................................................................................................................. 22

Table 13 – Bus-Matchings ............................................................................................................................................................................................. 24

Table 14 – MTYPE[1:0] Configurations .......................................................................................................................................................................... 25

Table 15 – Parameters affected by I/O selection ............................................................................................................................................................. 25

FEBRUARY 10, 2009

IDT72T6480 2.5V, SEQUENTIAL FLOW-CONTROL DEVICE

x12, x24, x48 BIT WIDE CONFIGURATION

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

List of Figures

Figure 1. Sequential Flow-Control Device Block Diagram ................................................................................................................................................ 5

Figure 2a. Configuration 1 - Two Chip Solution .............................................................................................................................................................. 13

Figure 2b. Configuration 2 - Two Chip Solution .............................................................................................................................................................. 13

Figure 2c. Configuration 3 - Three Chip Solution ........................................................................................................................................................... 13

Figure 2d. Configuration 4 - Three Chip Solution ........................................................................................................................................................... 13

Figure 2e. Configuration 5 - Three Chip Solution ........................................................................................................................................................... 13

Figure 2f. Configuration 6 - Four Chip Solution .............................................................................................................................................................. 13

Figure 2g. Configuration 7 - Five Chip Solution .............................................................................................................................................................. 13

Figure 3. Memory Interface Connection (Single Chip) .................................................................................................................................................... 17

Figure 4. Memory Interface Connection (Two Chip) ....................................................................................................................................................... 17

Figure 5a. AC Test Load ................................................................................................................................................................................................ 29

Figure 5b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 29

Figure 6. Master Reset and Initialization ......................................................................................................................................................................... 32

Figure 7. Partial Reset ................................................................................................................................................................................................... 33

Figure 8. Write First Word Cycles - IDT Standard Mode ................................................................................................................................................. 34

Figure 9. Write First Word Cycles - FWFT Mode ............................................................................................................................................................ 34

Figure 10. Empty Boundary - IDT Standard Mode ........................................................................................................................................................ 35

Figure 11. Empty Boundary - FWFT Mode .................................................................................................................................................................... 35

Figure 12. Full Boundary - IDT Standard Mode ............................................................................................................................................................ 36

Figure 13. Full Boundary - FWFT Mode ....................................................................................................................................................................... 36

Figure 14. Output Enable ............................................................................................................................................................................................... 37

Figure 15. Read Chip Select ......................................................................................................................................................................................... 37

Figure 16. Write Chip Select .......................................................................................................................................................................................... 37

Figure 17. Bus-Matching Configuration - x48 In to x24 Out - IDT Standard Mode .......................................................................................................... 38

Figure 18. Bus-Matching Configuration - x48 In to x12 Out - IDT Standard Mode .......................................................................................................... 38

Figure 19. Bus-Matching Configuration - x24 In to x48 Out - IDT Standard Mode .......................................................................................................... 39

Figure 20. Bus-Matching Configuration - x12 In to x48 Out - IDT Standard Mode .......................................................................................................... 39

Figure 21. Synchronous

PAE

Flag - IDT Standard Mode and FWFT Mode ................................................................................................................... 40

Figure 22. Synchronous

PAF

Flag - IDT Standard Mode and FWFT Mode ................................................................................................................... 40

Figure 23. Asynchronous Read and PAF Flag - IDT Standard Mode ............................................................................................................................. 41

Figure 24. Asynchronous Write and PAE Flag - IDT Standard Mode .............................................................................................................................. 41

Figure 25. Asynchronous Write and PAF Flag - IDT Standard Mode .............................................................................................................................. 41

Figure 26. Asynchronous Empty Boundary - IDT Standard Mode .................................................................................................................................. 42

Figure 27. Asynchronous Full Boundary - IDT Standard Mode ...................................................................................................................................... 42

Figure 28. Asynchronous Read and

PAE

Flag - IDT Standard Mode ............................................................................................................................ 42

Figure 29. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) ...................................................................................... 43

Figure 30. Reading of Programmable Flag Registers (IDT Standard and FWFT Modes) ............................................................................................... 43

Figure 31. Standard JTAG Timing ................................................................................................................................................................................. 44

Figure 32. JTAG Architecture ......................................................................................................................................................................................... 45

Figure 33. TAP Controller State Diagram ....................................................................................................................................................................... 46

Figure 34. Depth Expansion Configuration in IDT Standard Mode ................................................................................................................................. 49

Figure 35. Depth Expansion Configuration in FWFT Mode ............................................................................................................................................ 49

Figure 36. Width Expansion Configuration in IDT Standard Mode and FWFT Mode ....................................................................................................... 50

FEBRUARY 10, 2009

IDT72T6480L7-5BB相似产品对比

	IDT72T6480L7-5BB	IDT72T6480L7-5BBG
描述	IC flow-ctrl 48bit 7-5ns 324-bga	IC flow-ctrl 48bit 7-5ns 324-bga

推荐资源

出售一块ATRCB256RFR2-XPRO无线评估套件: 出售一块ATRCB256RFR2-XPRO无线评估套件，价格200，包邮。 qq:542370181 577719577720 产品介绍： ATRCB256RFR2-XPRO是Atmel推出的一款基于Atmega256RFR2无线微控制器产品 ......; annysky2012 淘e淘

TMS320F2812驱动无法连接: 不知道为什么，下载的驱动无法连接，安装总是不成功。。。。。仿真器就连接不上？？？大侠指点指点啊，台式机上没有问题，可是在笔记本上安装就出现了这个问题，。。。。。...; gaoxiao 微控制器 MCU

Intersil手持RFID阅读器解决方案: 在RFID系统中，信号接收设备一般叫做阅读器(或读卡器)。阅读器的基本功能就是提供与标签进行数据传输的接口。Intersil推出了手持RFID阅读器解决方案。...; JasonYoo 模拟电子

Linux0.11内核源码解析: 附件是Linux0.11的内核源码详细解析！希望对大家有用！...; 阳依草 ARM技术

易电源之评价[看资料玩游戏]: 逛论坛，偶发现了“玩游戏，体验易电源，赢取800元TI手持POS机开发套件”活动，大概看了活动规则，心动不如行动，参加了，满分收场。附图： 108161 游戏开始的时候，给我感觉就 ......; GONGHCU 模拟与混合信号

华邦LDRO程序在编程时是否会被擦除: 最近我在做华邦单片机编程，听说可ISP编程，于是兴奋之余按照说明书尝试了一番。首先保证串口没问题。下载LDROM（用编程器）进入ＣＰＵ后，打开ISP软件。写CPU配置，看到了硬件ISP进入使能P2. ......; yyjgoal 嵌入式系统

单片机STM32的启动文件详解--学习笔记

　　启动文件简介　　启动文件由汇编编写，是系统上电复位后第一个执行的程序。主要做了以下工作：　　1、初始化堆栈指针SP=_initial_sp 　　2、初始化PC 指针=Reset_Handler 　　3、初始化中断向量表　　4、配置系统时钟　　5、调用C 库函数_main 初始化用户堆栈，从而最终调用main 函数去到C 的世界　　查找ARM 汇编指令　　在讲解启动代码的时候，会涉...[详细]
韩企抱团，能否破解电池困境？

从全球领先到失去市场，韩国电池厂一直想要夺回失去的市场和尊严，但是面对以宁德时代和比亚迪为代表的中国电池厂商，却难以形成真正的竞争。根据统计，今年上半年，仅宁德时代和比亚迪就占全球电动汽车电池销量的 55%以上，高于 2024 年同期的53%。与此同时，韩国电池厂商LG Energy、SK On和三星SDI的合计市场份额下降至16.4%，比去年同期下降5.4%。虽然韩...[详细]
450Wh/kg！融捷集团发布第二代硫化物全固态电池

当固态电池行业仍在为电动汽车的“终极方案”进行漫长的技术马拉松时，部分企业已开始寻找更切近的商业化落地场景。近日，融捷集团旗下的融捷能源科技有限公司（以下简称“融捷能源”）正式推出其第二代全固态硫化物电池，能量密度达到450 Wh/kg。固态电池迈向实处，三赛道精准卡位 2025年，全球固态电池产业进入了一个关键的“去芜存菁”阶段。在经历多轮资本与产业的热潮起伏后，市场正...[详细]
目前电动汽车还存在哪些方面的安全隐患

随着购买新能源车型的消费者越来越多，电动车的安全性也成为了大家的焦点。尤其是在一系列电动车自燃事件之后，安全性这个话题也被推到了风口浪尖。那么电动车在电池方面存在着哪些隐患呢？一、冷却系统，新能源车型尤其是纯电动车型，是依靠电能作为补给。但电能并没有流入的冷却系统，所以在高温的条件下，电动车极容易发生自燃的事故。即便是现在很多新能源车型采用了水冷，但安全隐患依然存在。二、挤压碰撞，电...[详细]
新能源动力电池“三高”关键材料与技术分析和研究

前段时间参加了中国化学会第四届能源化学论坛学习了关于高比能高安全电池相关信息，再次总结和大家分享。全球新能源汽车（纯电和插混）销售量，2023年为1465万辆，2024年1823万辆。中国新能源汽车发展，迈入全球化的高质量发展新阶段，2023年新能源汽车累计销量950万辆，全球占比达到64.8，2024年累计销量达到1286万辆，全球占比70.5%。 2024年全球锂电池产量达...[详细]
苹果首款折叠 iPhone 曝料：配自研 C2 基带芯片

8 月 25 日消息，彭博社的马克・古尔曼昨日（8 月 24 日）发布博文，曝料称苹果将于 2026 年推出其首款折叠手机（下文简称 iPhone Fold），一方面会明显减少屏幕折痕，另一方面将搭载其自研的 C2 基带芯片，并采用无 SIM 卡设计、Touch ID 解锁，测试机有黑、白两色。苹果为尽量减少折痕的视觉影响，决定将屏幕触控感应层由 on-cell 技术改为 in-cell 技术...[详细]
stm32串口学习笔记

　　stm32作为现在嵌入式物联网单片机行业中经常要用多的技术，相信大家都有所接触，今天这篇就给大家详细的分析下有关于stm32的出口，还不是很清楚的朋友要注意看看了哦，在最后还会为大家分享有些关于stm32的视频资料便于学习参考。　　什么是串口　　UART : Universal Asynchronous Receiver/Transmitter 通用异步收发器　　USART : Uni...[详细]
“2025年7月中国充电桩增至1669.6万个，桩车比1:1.8满足新能源车增长”

8月22日，国家能源局发布最新数据，截至2025年7月底，我国电动汽车充电基础设施总数达到1669.6万个，同比增长53%。其中，公共充电设施为420.2万个，同比增长38%；私人充电设施为1249.4万个，同比增长58.8%。今年上半年，新能源汽车国内销量为587.8万辆，充电基础设施与新能源汽车的快速增长保持同步，桩车增量比为1:1.8，表明充电基础设施建设基本能够满足新能源汽车的快速发展需...[详细]
STM32单片机的学习方法（方法大体适用所有开发版入门）

1，一款实用的开发板。这个是实验的基础，有时候软件仿真通过了，在板上并不一定能跑起来，而且有个开发板在手，什么东西都可以直观的看到，效果不是仿真能比的。但开发板不宜多，多了的话连自己都不知道该学哪个了，觉得这个也还可以，那个也不错，那就这个学半天，那个学半天，结果学个四不像。倒不如从一而终，学完一个在学另外一个。 2，两本参考资料，即《STM32 参考手册》和《Cortex-M3 权威指南》。...[详细]
基于视觉的智能电子宠物

　　1 创意来源　　随着电子技术的进一步发展，电子宠物逐渐走入人们的家庭生活中，目前市面上相对成熟的电子宠物主要有两大类：一类是生活在电子设备中的虚拟宠物，没有任何的机械结构，纯粹通过电子设备与之进行交互;另一类是具有一定机械机构的电子宠物，具有触觉等功能，但由于其与逼真宠物外形想像的特性，交互方式也相对缺乏。　　如今感知计算技术大为盛行，它重新定义了人与设备的沟通方式，通过更适合人类的沟通...[详细]
一夜只耗一度电是真的吗？

　　随着科学的发展，变频技术的使用也越来越广泛，不管是工业设备上还是家用电器上都会使用到变频技术。其中变频空调近几年更是被炒的很火爆，变频空调具有噪音低省电等优点，更有商家打出变频空调“一夜只耗一度电”的广告语，这是真的吗? 　　变频空调的核心是变频控制器和变频电机，变频空调的能效如何，很大程度上由它们决定，因此要提高变频空调的能效呢，核心是提高空调变频控制器和变频电机的效率，那么问题来了如...[详细]
Peltier冷却器在智能汽车前照灯系统的应用

据外媒报道，Laird Thermal Systems公司推出HiTemp ET系列Peltier冷却器模块，可在高温下工作，为敏感电子器件提供现场冷却。在智能汽车前照灯系统中，数字光处理（DLP）技术的应用越来越多。采用这种技术，可以使车前面的光线更加清晰明亮。汽车前照灯系统可在110°C的高温下工作，而DLP器件的最高工作温度只有70℃，超过温限可能会产生故障或导致运行停止。采用HiT...[详细]
MCX E系列5V MCU发布：应对严苛环境，保障系统安全

MCX E系列是恩智浦丰富的MCX产品组合中最注重可靠性与安全性的系列。随着该系列的推出，恩智浦进一步丰富了其5V兼容的MCU产品线，为从3V到5V的设计提供一致的开发体验，帮助工程师在复杂环境中打造高可靠性的系统。随着边缘应用所处的环境日益严苛，对微控制器的韧性也提出了更高要求。MCX E系列应运而生，基于 Arm ® Cortex ® -M4F内核，专为在电气和热环境极端复杂的场景中...[详细]
Teletrac Navman推出Multi IQ多摄像头行车记录仪

Teletrac Navman推出Multi IQ行车记录仪，这是一款基于云端、专为大型商用车运营商打造的解决方案。它最多可连接五个摄像头，覆盖车辆内部、侧面、后部等区域，配合内置的高清双前置和驾驶员侧行车记录仪，解决了大型车辆盲点问题。图片来源： Teletrac 该记录仪运用先进人工智能分析技术，能检测疲劳驾驶、分心驾驶等事件，并以高清格式记录。其集成于Teletrac Navm...[详细]
单片机脚本语言-移植lua到stm32-MDK

Lua简单介绍 Lua 是一个小巧的脚本语言。作者是巴西人。该语言的设计目的是为了嵌入应用程序中，从而为应用程序提供灵活的扩展和定制功能。 Lua脚本能够非常easy的被C/C++ 代码调用，也能够反过来调用C/C++的函数，这使得Lua在应用程序中能够被广泛应用。不只作为扩展脚本，也能够作为普通的配置文件，取代XML,Ini等文件格式，而且更easy理解和维护。 Lua的目标是成为一个非常...[详细]

器件捷径: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

热门器件

开源项目推荐更多

热门活动更多

热门文章更多

技术资料推荐更多