SDC-14610/15 Series
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TM
Three Channel 14- and 16-Bit
Tracking S/D Converters
FEATURES
•
Synthesized Reference Option
•
Fixed 14- or 16-Bit Resolution
•
Small Size 36-Pin DDIP Package
•
Three Independent Converters
•
Low Cost per Channel
•
Velocity Output Eliminates
Tachometer
•
Optional BIT Output (LOS and LOR)
•
High Reliability Single Chip
Monolithic
•
-55°C to +125°C Operating
Temperature Range
DESCRIPTION
The SDC-14610/15 Series are small low cost three channel synchro-
or resolver-to-digital converters. The SDC-14610 Series is fixed at 14
bits, the SDC-14615 at 16 bits. The three channels are independent
tracking types but share digital output pins and a common reference.
The SDC-14610/15 “S” option offers synthesized reference circuitry
to correct for phase shifts between the reference and the signal volt-
age.
The velocity output (VEL) from the SDC-14610/15 Series, which can
be used to replace a tachometer, is a 4 V signal referenced to ground
with a linearity of 1% of output voltage.
A BIT output is optional and is a logic line that indicates LOS (Loss
Of Signal) or excessive converter error and LOR (Loss Of Reference
- option “S” only). Due to pin limitations this option will exclude the
velocity output. (See option “T”.)
SDC-14610/15 Series converters are available with operating tem-
perature ranges of 0°C to +70°C and -55°C to +125°C, and MIL-PRF-
38534 processing is available.
•
MIL-PRF-38534 Processing Available
APPLICATIONS
With its low cost, small size, high accuracy, and versatile perfor-
mance, the SDC-14610/15 Series converters are ideal for use in
modern high-performance military and industrial position control sys-
tems. Typical applications include radar antenna positioning, naviga-
tion and fire control systems, motor control, and robotics.
FOR MORE INFORMATION CONTACT:
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Technical Support:
1-800-DDC-5757 ext. 7382
©
1998, 1999 Data Device Corporation
Data Device Corporation
www.ddc-web.com
+REF
-REF
R
OPTIONAL
BIT
REFERENCE CONDITIONER
LOS / LOR
BIT
DETECTOR
ERROR
R
I
GAIN
DEMODULATOR
C
I
"S" OPTION
SYNTHESIZED REFERENCE
S1
S2
S3
S4
INPUT OPTION
CONTROL
TRANSFORMER
VEL
HYSTERESIS
INTEGRATOR
2
14/16-BIT
UP/DOWN
COUNTER
VCO & TIMING
DATA LATCH
SDC-14610/15 Series
8
EM DATA
EL
INH (Common)
FIGURE 1. SDC-14610/15 BLOCK DIAGRAM (ONE CHANNEL)
TABLE 1. SDC-14610/15 SPECIFICATIONS
These specs apply over the rated power supply, temperature, and reference fre-
quency ranges; 10% signal amplitude variation, and 10% harmonic distortion.
(Values are for each channel unless stated otherwise.)
TABLE 1. SDC 14610/15 SPECIFICATIONS (CONT.)
PARAMETER
DIGITAL INPUT/OUTPUT
(Cont.)
OUTPUTS
Parallel Data [1-14(16)]
UNIT
VALUE
Logic 1 = High Impedance
Data High Z within 100 ns
Common To All Channels
8 parallel lines; 2 bytes natural
binary angle, positive logic
Logic 0 = BIT condition
±100 LSBs of error with a filter
of 500 µs or LOS / (LOR-”S” only)
EACH CHANNEL
50 pF +
Logic 0; 1 TTL load, 1.6 mA at
0.4 V max
Logic 1; 10 TTL loads, -0.4 mA
at 2.8 V min
Logic 0; 100 mV max driving
Logic 1; +5 V supply minus
100 mV min driving
“S”
Device Type
OPTION
60 HZ
400 HZ
47-5 k
15
830
0.17
5k
29
14.5
14
16
1.25
1
18
1100
360-5 k
103
53k
1.33
40k
230
115
14
16
1 k-5 k
150
110k
2.47
44.4k
333
166
16
2.5
2
610
232
PARAMETER
RESOLUTION
ACCURACY
REPEATABILITY
DIFFERENTIAL LINEARITY
REFERENCE INPUT
Type
Voltage Range
Frequency
Input Impedance
single ended
differential
Common Mode Range
Option “S”
Voltage Range
Frequency
Input Impedance
single ended
differential
Common Mode Range
±Sig/Ref Phase Shift
SIGNAL INPUT
CHARACTERISTICS
90 V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common Mode Voltage
11.8 V Synchro Input (L-L)
Zin line-to-line
Zin line-to-ground
Common Mode Voltage
11.8 V Resolver Input (L-L)
Zin line-to-line
Zin line-to-ground
Common Mode Voltage
2 V Direct Input (L-L)
Voltage Range
Max Voltage No Damage
Input Impedance
2 V Resolver Input (L-L)
Zin single ended
Zin differential
Common Mode Voltage
DIGITAL INPUT/OUTPUT
Logic Type
Inputs
UNIT
Bits
Min
LSB
LSB
14
4 +1 LSB
VALUE
16
2 or 4 +1 LSB
1 +1 LSB (“S” only*)
1 max
1 max
(+REF, -REF ),
COMMON TO ALL CHANNELS
DIFFERENTIAL
bits
Built-In-Test (BIT)
(Optional)
Vrms
Hz
2 & 11.8 V UNITS 90 V UNIT
2-35
10-130
360-5000
see note **
270k min
540k min
200,
300 transient
—
—
—
—
—
—
—
Drive Capability
TTL
Ohm
60k
Ohm
120k
Vpeak 50,100 transient
CMOS
DYNAMIC
CHARACTERISTICS
Each Channel
Vrms
Hz
Ohm
Ohm
Vpeak
deg.
2-35
1k-5k
40k
80k
50,100 transient
45 max
EACH CHANNEL
(Not Available on “S” option)
123k
80k
180 max
(Not Available on “S” option)
52k
34k
30 max
140k
70k
30 max
(Not Available on “S” option)
2 nom, 2.3 max
25 cont, 100 pk transient
20 M//10 pF min
(“S” option only)
11k
22k
4.9 max
TTL/CMOS compatible
Logic 0 = 0.8 V max
Logic 1 = 2.0 V min
Loading (per channel) =10 µa
max P.U. current source to
+5 V //5 pF max
CMOS transient protected
EACH CHANNEL
Logic 0 inhibits; Data
stable within 0.5 µs
Logic 0 enables; Data stable
within 150 ns
Ohm
Ohm
V
Ohm
Ohm
V
Ohm
Ohm
V
Vrms
V
Ohm
Ohm
Ohm
V
Input Frequency
Hz
Bandwidth(Closed Loop)
Hz
Ka
1/s
2
A1
1/s
A2
1/s
A
1/s
B
1/s
Resolution
bits
Tracking Rate
typical
rps
minimum
rps
Acceleration (1 LSB lag)
deg/s
2
Settling Time (179° step
msec
max)
VELOCITY
CHARACTERISTICS
Polarity
±V
Voltage Range(Full Scale)
rps/FS
Voltage Scaling
±%
Scale Factor
ppm/°C
Scale Factor TC
±%
Reversal Error
±%
Linearity
mV
Zero Offset
µV/°C
Zero Offset TC
kOhm
Load
(Vp/V)%
Noise
POWER SUPPLIES
Nominal Voltage
Voltage Range
Max Volt. w/o Damage
Current (Ea.)
TEMPERATURE RANGE
Operating
-30X
-10X
Storage
PHYSICAL
CHARACTERISTICS
Size
Weight
Notes:
0.31 10 2.5
0.25 8
2
4.5 1160 290
2500 140 320
EACH CHANNEL
Positive for increasing angle
4.5 typ, 4 min
10
10 typ
20 max
100 typ 200 max
1 typ
2 max
0.5 typ 1 max
5 typ
10 max
15 typ
30 max
20 max
1 typ
2 max
TOTAL DEVICE
+5
-5
5
10
+7
-7
36 typ, 51 max
V
±%
V
mA
°C
°C
°C
0 to +70
-55 to +125
-65 to +150
Inhibit (lNH)(common)
Enable Bits 1 to 8 (EM)
Enable Bits 9 to 14(16) (EL)
in
(mm)
oz(g)
1.70 x 0.78 x 0.21
(43.2 x 19.8 x 5.3)
0.66(18.7)
* Applies to “S” Option only
** 47 - 5k for 90 V, 60 Hz; 360 - 5k for 90 V, 400 Hz
Data Device Corporation
www.ddc-web.com
3
SDC-14610/15 Series
THEORY OF OPERATION
The SDC-14610/15 Series of converters are based upon a sin-
gle chip CMOS custom monolithic. They are implemented using
the latest IC technology which merges precision analog circuitry
with digital logic to form a complete high performance tracking
resolver-to-digital converter.
FIGURE 1 is the Functional Block Diagram of the SDC-14610/15
Series. The converter operates with ±5 VDC power supplies.
Analog signals are referenced to analog ground, which is at
ground potential. The converter is made up of three main sec-
tions; an input front-end, a converter, and a digital interface. The
converter front-end differs for synchro, resolver and direct inputs.
An electronic Scott-T is used for synchro inputs, a resolver con-
ditioner for resolver inputs and a sine and cosine voltage follow-
er for direct inputs. These amplifiers feed the high accuracy
Control Transformer (CT). Its other input is the 14-bit digital angle
φ.
Its output is an analog error angle, or difference angle,
between the two inputs. The CT performs the ratiometric trigono-
metric computation of SINθCOSφ - COSθSINφ = SIN(θ -
φ)
using
amplifiers, switches, logic and capacitors in precision ratios.
The converter accuracy is limited by the precision of the com-
puting elements in the CT. In these converters, ratioed capacitors
are used in the CT instead of more conventional precision
ratioed resistors. Capacitors used as computing elements with
op-amps need to be sampled to eliminate voltage drifting.
Therefore, the circuits are sampled at a high rate to eliminate this
drifting and at the same time to cancel out the op-amp offsets.
The error processing is performed using the industry standard
technique for type II tracking R/D converters. The DC error is
integrated yielding a velocity voltage which, in turn, drives a volt-
age controlled oscillator (VCO). This VCO is an incremental inte-
grator (constant voltage input to position rate output) which,
together with the velocity integrator, forms a type II servo feed-
back loop. A lead in the frequency response is introduced to sta-
bilize the loop and another lag at higher frequency is introduced
to reduce the gain and ripple at the carrier frequency and above.
The components of gain coefficient are error gradient, integrator
gain, and VCO gain. These can be broken down as follows:
- Error Gradient = 0.011 volts per LSB (CT + Error Amp + Demod)
- Integrator Gain =
- VCO Gain =
1
volts per second per volt
R
i
C
i
1
LSBs per second per volt
1.25 R
v
C
v
GENERAL SETUP CONSIDERATIONS
The following recommendations should be considered when
connecting the SDC-14610/15 Series converters:
1) Power supplies are ±5 VDC. For lowest noise performance it
is recommended that a 0.1 µF or larger cap be connected
from each supply to ground near the converter package.
2) Direct inputs are referenced to AGND.
3) Connect pin 5 (GND) to pin 6 (AGND) close to the hybrid.
INHIBIT AND ENABLE TIMING
The Inhibit (INH) signal is used to freeze the digital output angle
in the transparent output data latch while data is being trans-
ferred. Application of an Inhibit signal does not interfere with the
continuous tracking of the converter. As shown in FIGURE 3,
angular output data is valid 500 nanoseconds maximum after the
application of the low-going inhibit pulse.
Output angle data is enabled onto the tri-state data bus in six
bytes. The Enable MSB (EM-A, EM-B, or EM-C) is used for the
most significant 8 bits and Enable LSB (EL-A, EL-B, or EL-C) is
used for the least significant bits. As shown in FIGURE 4, output
data is valid 150 nanoseconds maximum after the application of
a low-going enable pulse. The tri-state data bus returns to the
high impedance state 100 nanoseconds maximum after the ris-
ing edge of the enable signal.
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined
from its functional block diagram and its Bode plots (open and
closed loop); these are shown in FIGURES 1 and 2 respectively.
-1
2d
b/
The open loop transfer function is as follows:
2
GAIN = 4
t
oc
(CRITICALLY DAMPED)
2A
ω
(rad/sec)
10B
- GAIN = 0.4
f
3db
= BW =
2 A (Hz)
π
A
Open Loop Transfer Function =
S
2
(
+ 1
)
S
(
10B + 1
)
S
B
OPEN LOOP
B
A
(B=A/2)
-6
db
/oc
t
where A is the gain coefficient
and B is the frequency of lead compensation
CLOSED LOOP
2A
2 2A
ω
(rad/sec)
FIGURE 2. BODE PLOTS
Data Device Corporation
www.ddc-web.com
4
SDC-14610/15 Series
BIT, BUILT-IN-TEST (“T” OPTION)
This output is a logic line that will flag an internal fault condition,
or LOS (Loss-Of-Signal). The internal fault detector monitors the
internal error and, when it exceeds ±100 LSBs, will set the line
to a logic 0; this condition will occur during a large-step input and
will reset to a logic 1 after the converter settles out. (The error
voltage is filtered with a 500 µs filter) BIT will set for an overve-
locity condition because the converter loop can’t maintain
input/output sync. BIT will also be set if a total LOS (loss of all
signals) occurs or an LOR (loss of reference - “S” option only)
occurs.
The condition is artificial, as a “real” synchro or resolver cannot
change its output 180° instantaneously. The condition is most
often noticed during wraparound verification tests, simulations,
or troubleshooting.
SYNTHESIZED REFERENCE
The synthesized reference section (“S” option) eliminates errors
due to phase shift between the reference and signal inputs.
Quadrature voltages in a resolver or synchro are by definition the
resulting 90° fundamental signal in the nulled out error voltage
(e) in the converter. Due to the inductive nature of synchros and
resolvers, their output signals lead the reference input signal (RH
and RL). When an uncompensated reference signal is used to
demodulate the control transformer’s output, quadrature volt-
ages are not completely eliminated. As shown in FIGURE 1, the
converter synthesizes its own internal reference signal based on
the SIN and COS signal inputs. Therefore, the phase of the syn-
thesized (internal) reference is determined by the signal input,
resulting in reduced quadrature errors. The synthesized refer-
ence circuit also eliminates the 180 degree false error null hang up.
ENABLE
NO FALSE 180° HANGUP
This feature eliminates the “false 180° reading” during instanta-
neous 180° step changes; this condition most often occurs when
the input is “electronically switched” from a digital-to-synchro
converter. If the “MSB” (or 180° bit) is “toggled” on and off, a
converter without the “false 180° reading” feature may fail to
respond.
INHIBIT
DATA
FIGURE 3. INHIBIT TIMING
;;;;;;
500 ns MAX
DATA
VALID
DATA
HIGH Z
FIGURE 4. ENABLE TIMING
DOT
IDENTIFIES
PIN 1
; ;
150 ns MAX
DATA
VALID
1.700 ±0.005
(43.2 ±0.13)
BOTTOM VIEW
100 ns MAX
HIGH Z
TABLE 2. PINOUTS (36 PIN) (SEE NOTE 1)
1 S1A(S)
2 S2A(S)
3 S3A(S)
4 N.C.
5 GND
6
S1A(R)
S2A(R)
S3A(R)
S4A(R)
N.C.
36
VEL A (Velocity Output)
(see Note 2)
+COSA(D) 36 EM-A (Enable MSBs)
+SINA(D)
N.C.
34 EL-A (Enable LSBs)
33 INH (Inhibit)
32
VEL B (Velocity Output)
(see Note 2)
0.775 ±0.005
(19.7 ±0.13)
0.09 ±0.01
(2.3 ±0.25)
(Ground)(see Note 4)
0.600 ±0.005
(15.2 ±0.13)
AGND (Analog Ground)
(see Note 4)
S1B(R)
S2B(R)
S3B(R)
S4B(R)
N.C.
+SINB(D)
N.C.
31 EM-B (Enable MSBs)
30 EL-B (Enable LSBs)
28 Bit 7/Bit 15 (see Note 3)
27 Bit 6/Bit 14
26 Bit 5/Bit 13
25 Bit 4/Bit 12
SEATING
PLANE
0.10 ±0.01
(2.5 ±0.3)
1.895 ±0.005
(48.1 ±0.13)
0.21 MAX
(5.3)
SIDE VIEW
0.086 TYP
RADIUS
7 S1B(S)
8 S2B(S)
9 S3B(S)
10 N.C.
+COSB(D) 29 Bit 8/Bit 16 (see Note 3)
11 -5 V (Power Supply)
12 +5 V (Power Supply)
13 S1C(S)
14 S2C(S)
15 S3C(S)
16 N.C.
S1C(R)
S2C(R)
S3C(R)
S4C(R)
N.C.
+SINC(D)
N.C.
24 Bit 3/Bit 11
22 Bit 1/Bit 9
VEL C (Velocity Output)
21
(see Note 2)
20 EL-C (Enable LSBs)
19 EM-C (Enable MSBs)
0.015 MAX
(0.39)
0.25 MIN
(6.4)
0.055 (1.4)
RAD TYP
0.100 TYP(2.54)
TOL. NON-
CUMULATIVE
0.018 (0.46)
DIAM TYP
+COSC(D) 23 Bit 2/Bit 10
17 -REF (-Reference Input)
18 +REF (+Reference Input)
Notes: 1. (S) = Synchro; (R) = Resolver; (D) = 2 V Resolver Direct
2. Replaced with BIT - “T” option
3. SDC-14615 Series only
4. Connect pin 5 (GND) to pin 6 (AGND) close to the hybrid
Notes:
1. Dimensions are in inches (millimeters).
2. Lead identification numbers are for reference only.
3. Lead clusters shall be centered within ±0.01 of outline dimensions. Lead spac-
ing dimensions apply only at seating plane.
4. Pin material meets solderability requirements to MIL-STD-202E, Method 208C.
5. Case is electrically floating.
FIGURE 5. SDC-14610/15 MECHANICAL OUTLINE
Data Device Corporation
www.ddc-web.com
5
SDC-14610/15 Series
嵌入式系统
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