3.3V 64/32K X 18
SYNCHRONOUS
FOURPORT™ STATIC RAM
Features
◆
◆
◆
IDT70V5388/78
◆
◆
◆
◆
◆
◆
◆
◆
True four-ported memory cells which allow simultaneous
access of the same memory location
Synchronous Pipelined device
– 64/32K x 18 organization
Pipelined output mode allows fast 200MHz operation
High Bandwidth up to 14 Gbps (200MHz x 18 bits wide x
4 ports)
LVTTL I/O interface
High-speed clock to data access 3.0ns (max.)
3.3V Low operating power
Interrupt flags for message passing
Width and depth expansion capabilities
Counter readback on address lines
R/
W
P1
UB
P1
CE
0P1
CE
1P1
LB
P1
OE
P1
◆
◆
◆
◆
◆
◆
◆
◆
◆
Counter wrap-around control
– Internal mask register controls counter wrap-around
– Counter-Interrupt flags to indicate wrap-around
Mask register readback on address lines
Global Master reset for all ports
Dual Chip Enables on all ports for easy depth expansion
Separate upper-word and lower-word controls on all ports
272-BGA package (27mm x 27mm 1.27mm ball pitch) and
256-BGA package (17mm x 17mm 1.0mm ball pitch)
Commercial and Industrial temperature ranges
JTAG boundary scan
MBIST (Memory Built-In Self Test) controller
Green parts available, see ordering information
Port - 1 Logic Block Diagram
(2)
0
1
1 /0
I/O
9P1
- I/O
17P1
I/O
0P1
- I/O
8P1
Port 1
I/O
Control
TRST
TMS
TCK
TDI
CLKMBIST
JTAG
Controller
MBIST
TDO
Addr.
Read
Back
Port 1
Readback
Register
MRST
A
0P1
- A
15P1
(1)
CNTRD
P1
MKRD
P1
MKLD
P1
CNTINC
P1
CNTLD
P1
CNTRST
P1
CLK
P1
MRST
CNTINT
P1
Port 1
Mask
Register
Priority
Decision
Logic
Port 1
Counter/
Address
Register
Port 1
Address
Decode
64KX18
Memory
Array
,
R/
W
P1
CE
0P1
CE
1P1
CLK
P1
Port 1
Interrupt
Logic
INT
P1
MRST
NOTE:
1. A
15
x is a NC for IDT70V5378.
2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
5649 drw 01
OCTOBER 2008
DSC-5649/5
1
©2008 Integrated Device Technology, Inc.
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V5388/78 is a high-speed 64/32Kx18 bit
synchronous FourPort RAM. The memory array utilizes
FourPort memory cells to allow simultaneous access of
any address from all four ports. Registers on control, data,
and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows sys-
tems to be designed with very short cycle times.
With an input data register and integrated burst
counters, the 70V5388/78 has been optimized for applica-
tions having unidirectional or bi-directional data flow in
bursts. An automatic power down feature, controlled by
CE
0
and CE
1
, permits the on-chip circuitry of each port to enter
a very low standby power mode.
The IDT70V5388/78 provides a wide range of func-
tions specially designed to facilitate system operations.
These include full-boundary, maskable address counters
with associated interrupts for each port, mailbox interrupt
flags on each port to facilitate inter-port communications,
Memory Built-In Self-Test (MBIST), JTAG support and an
asynchronous Master Reset to simplify device initializa-
tion. In addition, the address lines have been set up as I/O
pins, to permit the support of
CNTRD
(the ability to output the
current value of the internal address counter on the address
lines) and
MKRD
(the ability to output the current value of the
counter mask register). For specific details on the device
operation, please refer to the Functional Description and
subsequent explanatory sections, beginning on page 21.
2
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(4)
70V5388/78BG
BG-272
(2)
272-Pin BGA
Top View
(3)
09/25/02
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
.
LB
P1
V
DD
A
14
P1
V
SS
A
10
P1
A
7
P1
V
SS
A
3
P1
V
DD
A
0
P1
A
0
P2
V
DD
A
3
P2
V
SS
A
7
P2
A
10
P2
V
SS
A
14
P2
V
DD
LB
P2
2
I/O
17
P2
UB
P1
A
15
(1)
P1
A
12
P1
A
11
P1
A
8
P1
A
5
P1
A
4
P1
A
1
P1
INT
P1
INT
P2
A
1
P2
A
4
P2
A
5
P2
A
8
P2
A
11
P2
A
12
P2
A
15
(1)
P2
UB
P2
I/O
8
P1
3
I/O
15
P2
I/O
16
P2
CE
1
P1
A
13
P1
4
I/O
13
P2
I/O
14
P2
CE
0
P1
OE
P1
5
I/O
11
P2
I/O
12
P2
R/W
P1
V
DD
6
I/O
9
P2
I/O
10
P2
I/O
15
P1
V
SS
7
I/O
16
P1
I/O
17
P1
V
SS
8
I/O
14
P1
I/O
13
P1
V
SS
9
I/O
12
P1
I/O
11
P1
I/O
9
P1
V
DD
10 11 12
I/O
10
P1
TMS
I/O
10
P4
TDI
I/O
12
P4
I/O
11
P4
I/O
9
P4
V
DD
13 14 15 16 17 18 19 20
I/O
14
P4
I/O
13
P4
V
SS
I/O
16
P4
I/O
17
P4
V
SS
I/O
9
P3
I/O
10
P3
I/O
15
P4
V
SS
I/O
11
P3
I/O
12
P3
R/W
P4
V
DD
I/O
13
P3
I/O
14
P3
CE
0
P4
OE
P4
I/O
15
P3
I/O
16
P3
CE
1
P4
A
13
P4
I/O
17
P3
UB
P4
A
15
(1)
P4
A
12
P4
A
11
P4
A
8
P4
A
5
P4
A
4
P4
A
1
P4
LB
P4
V
DD
A
14
P4
V
SS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
,
TCK
TDO
V
SS
V
DD
V
SS
V
SS
V
DD
V
SS
MKRD CNTRD
P1
P1
A
9
P1
A
6
P1
CNTINT
P1
CNTINC
P1
CNTRD MKRD
P4
P4
CNTINT
P4
CNTINC
P4
A
10
P4
A
7
P4
V
SS
A
3
P4
V
DD
A
0
P4
A
0
P3
V
DD
A
3
P3
V
SS
A
7
P3
A
10
P3
V
SS
A
14
P3
A
9
P4
A
6
P4
MKLD CNTLD
P1
P1
A
2
P1
CNTRST
P1
CNTLD MKLD
P4
P4
GND
(5)
V
DD
CLK
P1
GND
(5)
GND
(5)
GND
(5)
V
DD
A
2
P4
GND
(5)
GND
(5)
GND
(5)
GND
(5)
CLK
CNTRST
INT
P4
P4
P4
V
SS
CLK
P3
CNTRST
INT
P3
P3
CNTRST
V
SS
P2
GND
(5)
GND
(5)
GND
(5)
GND
(5)
A
2
P2
CLK
P2
GND
(5)
GND
(5)
GND
(5)
GND
(5)
A
2
P3
A
1
P3
A
4
P3
A
5
P3
A
8
P3
A
11
P3
A
12
P3
A
15
(1)
P3
UB
P3
I/O
8
P4
MKLD CNTLD
P2
P2
A
6
P2
A
9
P2
CNTINC
P2
CNTINT
P2
CNTLD MKLD
P3
P3
CNTINC
P3
CNTINT
P3
A
6
P3
A
9
P3
MKRD CNTRD
P2
P2
A
13
P2
CE
1
P2
I/O
7
P1
I/O
6
P1
OE
P2
CE
0
P2
I/O
5
P1
I/O
4
P1
V
DD
R/W
P2
I/O
3
P1
I/O
2
P1
V
SS
I/O
6
P2
I/O
1
P1
I/O
0
P1
V
SS
V
DD
V
DD
I/O
0
P2
I/O
2
P2
I/O
3
P2
V
SS
V
SS
V
DD
I/O
0
P3
I/O
2
P3
I/O
3
P3
V
DD
V
SS
V
SS
I/O
6
P3
I/O
1
P4
I/O
0
P4
V
DD
R/W
P3
I/O
3
P4
I/O
2
P4
CNTRD MKRD
P3
P3
OE
P3
CE
0
P3
I/O
5
P4
I/O
4
P4
A
13
P3
CE
1
P3
I/O
7
P4
I/O
6
P4
V
SS
I/O
8
P2
I/O
7
P2
V
SS
TRST
NC
V
SS
I/O
4
P3
I/O
5
P3
V
SS
I/O
8
P3
I/O
7
P3
I/O
4
P2
I/O
5
P2
MRST
CLKMBIST
V
DD
LB
P3
Y
I/O
1
P2
I/O
1
P3
1
2
3
4
5
6
7
8
9
10 11 12
13 14 15 16 17 18 19 20
5649 drw 03
NOTES:
1. A
15
x is a NC for IDT70V5378.
2. This package code is used to reference the package diagram.
3. This text does not indicate orientation of the actual part marking.
4. Package body is approximately 27mm x 27mm x 2.33mm, with 1.27mm ball-pitch.
5. Central balls are for thermal dissipation only. They are connected to device V
SS
.
3
6.42
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(2)
70V5388/78BC
BC-256
(3)
256-Pin BGA
(4)
Top View
09/25/02
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
R/W
P1
2
OE
P1
3
LB
P1
4
I/O
16
P2
5
I/O
13
P2
6
I/O
9
P2
7
I/O
14
P1
8
I/O
10
P1
9
I/O
9
P4
10
I/O
12
P4
11
I/O
16
P4
12 13 14
I/O
11
P3
15 16
UB
P4
I/O
15
P3
I/O
17
P3
CE
1
P4
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
A
15
(1)
P1
CE
1
P1
UB
P1
I/O
17
P2
I/O
14
I/O
10
P2
P2
I/O
15
P1
I/O
11
P1
TDI
TDO
TCK
I/O
13
I/O
17
I/O
12
P4
P4
P3
I/O
16
P3
LB
P4
R/W
P4
CE
0
P4
A
14
P1
A
13
P1
CE
0
P1
I/O
15
P2
I/O
12
P2
I/O
17
I/O
12
P1
P1
I/O
9
P1
I/O
11
P4
I/O
15
I/O
10
P4
P3
I/O
14
P3
OE
P4
A
15
(1)
P4
A
14
P4
A
10
P1
A
12
P1
A
11
P1
A
9
P1
I/O
11
P2
I/O
16
I/O
13
P1
P1
TMS
I/O
10
P4
I/O
14
P4
I/O
9
P3
I/O
13
P3
A
11
P4
A
12
P4
A
13
P4
A
7
P1
A
8
P1
A
6
P1
A
5
P1
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
V
DD
V
DD
V
SS
V
SS
V
DD
V
SS
P4
A
6
P4
A
7
P4
A
8
P4
A
10
P4
A
9
P4
A
3
P1
A
4
P1
A
2
P1
A
1
P1
V
DD
V
DD
V
DD
V
SS
INT
P1
A
1
P4
A
2
P4
A
3
P4
A
5
P4
A
4
P4
CLK
P1
A
0
P1
CNTRD
CNTINC
P1
P1
CNTLD
CNTINC
CNTRD
P4
P4
P4
A
0
P4
CLK
P4
V
SS
CLK
P2
CNTLD
CNTRST CNTINT
P1
P1
P1
MKLD
P1
CNTRST
MKRD
P4
INT
CNTINT
MKLD
P4
P4
P4
V
SS
CLK
P3
CNTRST
INT
P2
P2
CNTINT
MKRD
P2
P1
V
SS
V
SS
V
DD
V
DD
I/O
6
P2
V
SS
V
SS
V
SS
V
SS
CNTRST
P3
INT
CNTINT
MKLD
P3
P3
P3
CNTRD
MKRD
CNTINC
CNTLD MKLD
P2
P2
P2
P2
P2
V
SS
V
SS
V
SS
CNTLD
CNTINC
MKRD
P3
P3
P3
A
0
P3
CNTRD
P3
A
3
P2
A
4
P2
A
2
P2
A
1
P2
A
0
P2
V
DD
V
SS
V
DD
I/O
2
P2
V
SS
V
DD
V
DD
I/O
7
P3
V
DD
V
DD
I/O
2
P4
A
1
P3
A
3
P3
A
4
P3
A
2
P3
A
8
P2
A
9
P2
A
7
P2
A
6
P2
A
5
P2
V
DD
V
DD
V
DD
TRST
MRST
CLKMBIST
A
5
P3
A
7
P3
A
8
P3
A
6
P3
A
11
P2
A
12
P2
A
10
P2
I/O
5
P1
I/O
1
P1
I/O
3
P3
A
9
P3
A
11
P3
A
12
P3
A
10
P3
A
13
P2
A
14
P2
R/W
P2
I/O
7
P1
I/O
2
P1
I/O
7
P2
I/O
3
P2
I/O
0
P3
I/O
4
P3
I/O
8
P3
I/O
3
P4
I/O
6
P4
CE
0
P3
A
14
P3
A
13
P3
A
15
(1)
P2
CE
1
P2
UB
P2
I/O
8
P1
I/O
4
P1
I/O
0
P1
I/O
5
P2
I/O
1
P2
I/O
2
P3
I/O
6
P3
I/O
1
P4
I/O
5
P4
I/O
7
P4
UB
P3
CE
1
P3
A
15
(1)
P3
CE
0
P2
OE
P2
LB
P2
I/O
6
P1
I/O
3
P1
I/O
8
P2
I/O
4
P2
I/O
0
P2
I/O
1
P3
I/O
5
P3
I/O
0
P4
I/O
4
P4
I/O
8
P4
LB
P3
OE
P3
R/W
P3
1
2
3
4
5
6
7
8
9
10 11
12 13 14 15 16
5649 drw 04
NOTES:
1. A
15
x is a NC for IDT70V5378.
2. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
3. This package code is used to reference the package diagram.
4. This text does not indicate orientation of the actual part-marking.
4
IDT70V5388/78
3.3V 64/32K x 18 Synchronous FourPort™ Static RAM
Industrial and Commercial Temperature Ranges
Pin Definitions
Port 1
A
0P1
- A
15P1
(1)
I/O
0P1
- I/O
17P1
CLK
P1
Port 2
A
0P2
- A
15P2
(1)
I/O
0P2
- I/O
17P2
CLK
P2
Port 3
A
0P3
- A
15P3
(1)
I/O
0P3
- I/0
17P3
CLK
P3
Port 4
A
0P4
- A
15P4
(1)
I/O
0P4
- I/O
17P4
CLK
P4
Description
Address Inputs. In the
CNTRD
and
MKRD
operations, these pins serve
as outputs for the internal address counter and the internal counter mask
register respectively.
Data Bus Input/Output.
Clock Input. The maximum clock input rate is f
MAX
. The clock signal can
be free running or strobed depending on system requirements.
Master Reset Input.
MRST
is an asycnchronous input, and affects all
ports. It must be asserted LOW (MRST = V
IL
) at initial power-up. Master
Reset sets the internal value of all address counters to zero, and sets
the counter mask registers for each port to 'unmasked'. It also resets the
output flags for the mailboxes and the counter interrupts (INT =
CNTINT
= V
IH
) and deselects all registered control signals.
CE
0P2
, CE
1P2
CE
0P3
, CE
1P3
CE
0P4
, CE
1P4
Chip Enable Inputs. To activate any port, both signals must be asserted
to their active states
(CE
0
= V
IL
, CE
1
= V
IH
). A given port is disabled if
either chip enable is deasserted (CE
0
= V
IH
and/or CE
1
= V
IL
).
Read/Write Enable Input. This signal is asserted LOW (R/
W
= V
IL
) in
order to write to the FourPort memory array, and it is asserted HIGH
(R/W = V
IH
) in order to read from the array.
Lower Byte Select Input (I/O
0
- I/O
8
). Asserting this signal LOW (LB = V
IL
)
enables read/write operations to the lower byte. For read operations, this
signal is used in conjunction with
OE
in order to drive output data on the
lower byte of the data bus.
Upper Byte Select Input (I/O
9
- I/O
17
). Asserting this signal LOW (LB =
V
IL
) enables read/write operations to the upper byte. For read
operations, this signal is used in conjunction with
OE
in order to drive
output data on the upper byte of the data bus.
Output Enable Input. Asserting this signal LOW (OE = V
IL
) enables the
device to drive data on the I/O pins during read operation.
OE
is an
asychronous input.
Counter Load Input. Asserting this signal LOW (CNTLD = V
IL
) loads the
address on the address lines (A
0
- A
15
(1)
) into the internal address
counter for that port.
Counter Increment Input. Asserting this signal LOW (CNTINC = V
IL
)
increments the internal address counter for that port on each rising edge
of the clock signal. The counter will increment as defined by the counter
mask register for that port (default mode is to advance one address on
each clock cycle).
Counter Readback Input. When asserted LOW (CNTRD = V
IL
) causes that
port to output the value of its internal address counter on the address
lines for that port. Counter readback is independent of the chip enables
for that port. If the port is activated (CE
0
= V
IL
and CE
1
= V
IH
), during the
counter readback operation, then the data bus will output the data
associated with that readback address in the FourPort memory array
(assuming that the byte enables and output enables are also asserted).
Truth Table III indicates the required states for all other counter controls
during this operation. The specific operation and timing of this funcion is
described in detail in the text.
Counter Reset Input. Asserting this signal LOW
(CNTRST
= V
IL
) resets
the address counter for that port to zero.
Counter Interrupt Flag Output. This signal is asserted LOW (CNTINT =
V
IL
) when the internal address counter for that port 'wraps around' from
max address [(the counter will increment as defined by the counter mask
register for that port (default mode is to advance one address on each
clock cycle)] to address min. as the result of counter increment (CNTINT
= V
IL
). The signal goes LOW for one clock cycle, then automatically
resets.
5649 tbl 01
MRST
CE
0P1
, CE
1P1
R/W
PI
R/W
P2
R/W
P3
R/W
P4
LB
P1
LB
P2
LB
P3
LB
P4
UB
P1
UB
P2
UB
P3
UB
P4
OE
P1
OE
P2
OE
P3
OE
P4
CNTLD
P1
CNTLD
P2
CNTLD
P3
CNTLD
P4
CNTINC
P1
CNTINC
P2
CNTINC
P3
CNTINC
P4
CNTRD
P1
CNTRD
P2
CNTRD
P3
CNTRD
P4
CNTRST
P1
CNTRST
P2
CNTRST
P3
CNTRST
P4
CNTINT
P1
CNTINT
P2
CNTINT
P3
CNTINT
P4
5
6.42
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