Integrated
Circuit
Systems, Inc.
ICS9248-150
Frequency Generator for Multi-Processor Servers
Recommended Application:
ServerWorks Grand Champion Systems
Output Features:
•
8 - Differential CPU Clock Pairs @ 3.3V
•
1 - 3V 33MHz PCI clocks
•
1 - 48MHz clock
•
1 - Inverted 48MHz clock
•
1 - 14.318MHz reference output
Features:
•
Up to 200MHz frequency support
•
Support power management: Power Down Mode
•
Supports Spread Spectrum modulation: 0 to -0.5%
down spread.
•
Uses external 14.318MHz crystal
•
Select logic for Differential Swing Control, Test mode,
Tristate, Power down, Spread Spectrum.
•
External resistor for current reference
•
FS pins for frequency select
Key Specifications:
•
PCI Output jitter <500ps
•
CPU Output jitter <150ps
•
48MHz Output jitter <350ps
•
REF Output jitter < 1000ps
PCICLK
VDD48
FS0/48MHz
FS1/48MHz#
GND48
VDDCPU
CPUCLKT0
CPUCLKC0
GNDCPU
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT2
CPUCLKC2
GNDCPU
CPUCLKT3
CPUCLKC3
VDDCPU
REF
SPREAD#
GNDREF
X1
X2
VDDREF
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL100/133
GNDPCI
VDDA
GNDA
PD#
VDDCPU
CPUCLKT4
CPUCLKC4
GNDCPU
CPUCLKT5
CPUCLKC5
VDDCPU
CPUCLKT6
CPUCLKC6
GNDCPU
CPUCLKT7
CPUCLKC7
VDDCPU
MULTSEL0
MULTSEL1
GND
GNDI REF
I REF
VDDI REF
48-Pin SSOP and TSSOP
Functionality
SEL133/100
0
0
0
0
1
1
1
1
FS0
0
0
1
1
0
0
1
1
FS1
0
1
0
1
0
1
0
1
Function
Active 100MHz
100MHz Test Mode
100MHz Test Mode
Tristate all outputs
Active 133MHz
133MHz Test Mode
Active 200MHz
Reser ved
Block Diagram
PLL2
ICS9248-150
48MHz
48MHz#
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
REF
CPU
DIVDER
8
8
CPUCLKT (7:0)
CPUCLKC (7:0)
PCICLK
Analog Power Groups
VDD48, GND48 = 48MHz, PLL2
VDDA=VDD (core supply voltage 3.3V)
GNDA=Ground for core supply
PCI
DIVDER
Digital Power Group
VDDREF, GNDREF = REF, Xtal
PD#
SPREAD#
MULTSEL(1:0)
SEL100/133
FS(1:0)
Control
Logic
Config.
Reg.
I REF
0352F—03/29/06
ICS9248-150
General Description
ICS9248-150
is a main clock for ServerWorks Grand Champion Systems.
Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without
resorting to board design iterations or costly shielding.
ICS9248-150
employs a proprietary closed loop design,
which tightly controls the percentage of spreading over process and temperature variations.
Pin Configuration
PIN NUMBER
1
2, 6, 12, 18, 24,
31, 37, 43,
3
4
5, 9, 15, 21, 28,
34, 40, 47
33, 36, 39, 42, 16,
13, 10, 7
32, 35, 38, 41, 17,
14, 11, 8
19
20
22
23
25, 46
26
29, 30
44
27, 45
48
PIN NAME
PCICLK
VDD
FS0
48MHz
FS1
48MHz#
GND
CPUCLKT (7:0)
CPUCLKC (7:0)
REF
SPREAD#
X1
X2
VDDI REF
VDDA,
I REF
MULTSEL(1:0)
PD#
GNDI REF
GNDA
SEL100/133
TYPE
OUT
PWR
IN
OUT
IN
OUT
PWR
OUT
OUT
OUT
IN
X2 Cr ystal Input
PCI clock output
3.3V power supply
Frequency select pin
48MHz clock output
Frequency select pin
DESCRIPTION
Inver ted 48MHz clock output
Ground pins for 3.3V supply
"True" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
"Complementar y" clocks of differential pair CPU outputs. These
are current outputs and external resistors are required for
voltage bias.
Reference output 14.318MHz
Invokes Spread Spectrum functionality on the Differential host
clocks, Active Low
14.318MHz Cr ystal input
X1 Cr ystal Output 14.318MHz Cr ystal output
PWR
OUT
IN
IN
PWR
IN
Analog power supply 3.3V
This pin establishes the reference current for the CPUCLK
pairs. This pin takes a fixed precision resistor tied to ground in
order to establish the required current.
CPU swing select inputs
Invokes power-down mode. Active Low.
Analog Ground pins for 3.3V supply
CPU Frequency Select. Low=100MHz, High=133MHz
0352F—03/29/06
2
ICS9248-150
Truth Table
SEL
133/100
0
0
0
0
1
1
1
1
FS0
0
0
1
1
0
0
1
1
FS1
0
1
0
1
0
1
0
1
CPUCLK
MHz
100
100
100
Tristate
133
133
200
TCLK/2
PCICLK
MHZ
33
33
Disable
Tristate
33
33
33
TCLK/8
48
MHz
48
Disable
Disable
Tristate
48
Disable
48
TCLK/2
CPUCLK Buffer Configuration
Conditions
Iout
Vdd = nominal (3.30V)
Configuration
All combinations of
M0, M1 and Rr shown
in table below
All combinations of
M0, M1 and Rr shown
in table below
Load
Nominal test load for
given configuration
Nominal test load for
given configuration
Min
Max
-7% I nominal +7% I nominal
-12% I
nominal
+12% I
nominal
Iout
Vdd = 3.30 ± 5%
0352F—03/29/06
3
ICS9248-150
CPUCLK Swing Select Functions
MULTSEL0
0
0
0
0
1
1
1
1
MULTSEL1
0
0
1
1
0
0
1
1
Board Target
Trace/Term Z
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
Reference R,
Iref=
Vdd/(3*Rr)
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Output
Current
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
Voh @ Z,
Iref=2.32mA
0.71V @ 60
0.59V @ 50
0.85V /2 60
0.71V @ 50
0.56V @ 60
0.47V @ 50
0.99V @ 60
0.82V @ 50
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0.75V @ 30
0.62V @ 20
0.90V @ 30
0.75V @ 20
0.60 @ 20
0.5V @ 20
1.05V @ 30
0.84V @ 20
0352F—03/29/06
4
ICS9248-150
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . .
5.5 V
GND –0.5 V to V
DD
+0.5 V
0°C to +70°C
115°C
–65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Operating Supply
Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
1
SYMBOL
CONDITIONS
V
IH
V
IL
I
IH
V
IN
= V
DD
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
I
DD3.3OP
I
DD3.3PD
F
i
L
pin
C
IN
C
OUT
C
INX
T
STAB
T
REC
t
PZH
,t
PZL
t
PHZ
,t
PLZ
C
L
= 0 pF; Select @ 100 MHz
C
L
= 0 pF; Input address to VDD or GND
V
DD
= 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
CPU Freq. = 100/133 MHz
CPU Freq. = 200 MHz
CPU Freq. = 100/133 MHz
CPU Freq. = 200 MHz
Output enable delay (all outputs)
Output disable delay (all outputs)
MIN
2
V
SS
- 0.3
-5
-5
-200
TYP
MAX
V
DD
+ 0.3
0.8
5
UNITS
V
V
mA
mA
181
52
14.318
250
60
7
5
6
45
8
10.5
8
10.5
10
10
mA
mA
MHz
nH
pF
pF
pF
ms
ms
ms
ms
ns
ns
27
Clk Stabilization
1, 2
Clk Recovery
1, 3
Delay
1
1
2
1
1
Guaranteed by design, not 100% tested in production.
From VDD = 3.3V to 1% of target frequency
3
From deassertion of PD# to 1% of target frequency
0352F—03/29/06
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
