PRELIMINARY
ICS855011
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-2.5V/3.3V CML F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS855011 is a low skew, high perfor-
mance 1-to-2 Differential-to-2.5V/3.3V CML
HiPerClockS™
Fa n o u t B u f f e r a n d a m e m b e r o f t h e
HiPerClockS ™ family of High Perfor mance
Clock Solutions from IDT. The ICS855011
is characterized to operate from either a 2.5V or a
3.3V power supply. Guaranteed output and par t-to-
part skew characteristics make the ICS855011 ideal
for those clock distribution applications demanding
well defined perfor mance and repeatability.
F
EATURES
•
Two differential 2.5V/3.3V CML outputs
•
One differential PCLK, nPCLK input pair
•
PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
•
Output frequency: >3GHz
•
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
•
Output skew: 5ps (typical)
•
Part-to-part skew: TBD
•
Propagation delay: 242ps (typical)
•
Operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
•
-40°C to 85°C ambient operating temperature
•
Available in both standard (RoHS5) and lead-free (RoHS 6)
packages
ICS
B
LOCK
D
IAGRAM
PCLK
nPCLK
Q0
nQ0
Q1
nQ1
P
IN
A
SSIGNMENT
Q0
nQ0
Q1
nQ1
1
2
3
4
8
7
6
5
Vcc
PCLK
nPCLK
V
EE
ICS855011
8-Lead TSSOP
3mm x 3mm x 0.95mm package body
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product
characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifica-
tions without notice.
855011AG
1
REV. A JANUARY 16, 2008
PRELIMINARY
ICS855011
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-2.5V/3.3V CML F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5
6
7
8
Name
Q0, nQ0
Q1, nQ1
V
EE
nPCLK
PCLK
V
CC
Output
Output
Power
Input
Input
Power
Pullup
Type
Description
Differential output pair. CML interface levels.
Differential output pair. CML interface levels.
Negative supply pin.
Inver ting differential LVPECL clock input.
Positive supply pin.
Pulldown Non-inver ting LVPECL differential clock input.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
R
PULLDOWN
R
PULLUP
Parameter
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
75
75
Maximum
Units
kΩ
kΩ
855011AG
2
REV. A JANUARY 16, 2008
PRELIMINARY
ICS855011
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-2.5V/3.3V CML F
ANOUT
B
UFFER
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Storage Temperature, T
STG
(Junction-to-Ambient)
4.6V (CML mode, V
EE
= 0)
-0.5V to V
CC
+ 0.5 V
20mA
40mA
-65°C to 150°C
Operating Temperature Range, TA -40°C to +85°C
Package Thermal Impedance,
θ
JA
101.7°C/W (0 m/s)
NOTE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
to the device. These ratings are stress specifi-
cations only. Functional operation of product at
these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
affect product reliability.
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V; V
EE
= 0V
Symbol
V
CC
I
EE
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.375
Typical
3.3
50
Maximum
3.8
Units
V
mA
T
ABLE
3B. LVPECL DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V; V
EE
= 0V
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
PCLK
nPCLK
PCLK
nPCLK
Test Conditions
V
CC
= V
IN
= 3.8V
V
CC
= V
IN
= 3.8V
V
CC
= 3.8V, V
IN
= 0V
V
CC
= 3.8V, V
IN
= 0V
-5
-150
1
V
CC
Minimum
Typical
Maximum
150
5
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
0.3
Common Mode Input Voltage;
V
CMR
V
EE
+ 1.5
NOTE 1, 2
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is V
CC
+ 0.3V.
T
ABLE
3C. CML DC C
HARACTERISTICS
,
V
CC
= 2.375V
TO
3.8V; V
EE
= 0V
Symbol
V
OH
V
OUT
V
DIFF_OUT
R
OUT
Parameter
Output High Voltage; NOTE 1
Output Voltage Swing
Differential Output Voltage Swing
Output Source Impedance
Conditions
Minimum
V
CC
- 0.020
325
650
40
Typical
V
CC
- 0.010
400
800
50
60
Maximum
V
CC
Units
V
mV
mV
Ω
NOTE 1: Outputs terminated with 100
Ω
across differential output pair.
855011AG
3
REV. A JANUARY 16, 2008
PRELIMINARY
ICS855011
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-2.5V/3.3V CML F
ANOUT
B
UFFER
T
ABLE
4. AC C
HARACTERISTICS
,
V
CC
= 0V; V
EE
= -3.8V
TO
-2.375V
OR
V
CC
= 2.375
TO
3.8V; V
EE
= 0V
Symbol Parameter
f
MAX
Output Frequency
Propagation Delay; (Differential);
NOTE 1
Output Skew; NOTE 2, 4
Par t-to-Par t Skew; NOTE 3, 4
Output Rise/Fall Time
20% to 80%
Condition
Minimum
Typical
>3
242
5
TBD
140
Maximum
Units
GHz
ps
ps
ps
ps
ps
t
PD
t
sk(o)
t
sk(pp)
t
R
/t
F
odc
Output Duty Cycle
50
All parameters characterized at
≤
1GHz unless otherwise noted.
R
L
= 100
Ω
after each output pair.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
855011AG
4
REV. A JANUARY 16, 2008
PRELIMINARY
ICS855011
L
OW
S
KEW
, 1-
TO
-2
D
IFFERENTIAL
-
TO
-2.5V/3.3V CML F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
CML with Internal Pullup
+
3.3V ± 5%
or
2.5V ± 5%
GND
V
CC
Qx
SCOPE
V
CC
nPCLK
Float
GND
-
V
EE
V
PP
Cross Points
V
CMR
Power
Supply
PCLK
nQx
V
EE
O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
nQx
PART 1
Qx
nQy
PART 2
Qy
tsk(pp)
D
IFFERENTIAL
I
NPUT
L
EVEL
nQx
Qx
nQy
Qy
tsk(o)
P
ART
-
TO
-P
ART
S
KEW
O
UTPUT
S
KEW
nPCLK
80%
Clock
Outputs
80%
V
SW I N G
PCLK
nQ0, nQ1
Q0, Q1
t
PD
20%
t
R
t
F
20%
O
UTPUT
R
ISE
/F
ALL
T
IME
nQ0, nQ1
Q0, Q1
P
ROPAGATION
D
ELAY
t
PW
t
PERIOD
odc =
t
PW
t
PERIOD
x 100%
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
855011AG
5
REV. A JANUARY 16, 2008
嵌入式系统
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