Octal 2:1 and 1:2 Differential-to-LVDS
Multiplexer
General Description
The ICS854S54I-08 is an octal 2:1 and 1:2
Multiplexer. The device contains four individually
HiPerClockS™
controlled banks of LVDS outputs. The 2:1 Multiplexer
allows one of 2 inputs to be selected onto one output
pin and the 1:2 MUX switches one input to one of two
outputs. This device is useful for multiplexing multi-rate Ethernet
PHYs which have 100M bit and 1000M bit transmit/receive pairs
onto an optical SFP module which has a single transmit/receive pair.
See Application Section for further information.
ICS854S54I-08
DATA SHEET
Features
•
•
•
•
•
•
•
•
•
•
•
Four banks of three LVDS output pairs
Twelve differential data intputs
Serial 1
2
C Interface
Data pairs can accept the following differential input levels:
LVPECL, LVDS, CML
Maximum output frequency: 1.3GHz
Propagation delay: 1ns (maximum)
Additive phase jitter, RMS: 0.066ps (typical)
Part-to-part skew: 475ps (maximum)
Full 3.3V supply voltage
Available in both standard (R0HS 5) and lead-free (RoHS 6)
packages
-40°C to 85°C ambient operating temperature
ICS
The ICS854S54I-08 is optimized for ATCA backplane swtich
applications requiring very high performance and has a maximum
operating frequency of 1.3GHz. The device is packaged in a small,
10mm x 10mm TQFP package, making it ideal for use on
space-constrained boards.
Pin Assignment
GND
INC0
nINC0
INC1
nINC1
IND
INA1
nINA0
INA0
nINB
INB
nINA1
V
DD
SDA
SCLK
nIND
QA0
nQA0
GND
QA1
nQA1
V
DD
QB
nQB
nQF
QF
V
DD
nQE1
QE1
GND
nQE0
QE0
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
3
46
4
45
5
44
ICS854S54I-08
6
43
64-Lead TQFP, E-Pad
7
42
10mm x 10mm x 1.0mm
8
41
package body
9
40
10
Y package
39
11
38
Top View
12
37
13
36
14
35
1
2
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
INE1
nINE0
INE0
V
DD
ADR1
ADR0
GND
ING0
nING0
ING1
nING1
INH
nINF
INF
nINE1
nINH
QC0
nQC0
GND
QC1
nQC1
V
DD
QD
nQD
nQH
QH
V
DD
nQG1
QG1
GND
nQG0
QG0
ICS854S54AYI-08 FEBRUARY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS854S54I-08 Data Sheet
OCTAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Block Diagram
INB
nINB
INA0
nINA0
1
0
0
QA0
nQA0
INA1
nINA1
0
QB
nQB
1
QA1
nQA1
1
SEL_QB MODE_QAx
IND
nIND
SDA
SCL
ADR[1:0]
INC0
nINC0
1
0
0
2
QC0
nQC0
INC1
nINC1
0
IC
2
QD
nQD
1
QC1
nQC1
1
SEL_QD MODE_QCx
INF
nINF
INE0
nINE0
1
0
0
QE0
nQE0
INE1
nINE1
0
QF
nQF
1
QE1
nQE1
1
SEL_QF MODE_QEx
INH
nINH
ING0
nING0
1
0
0
QG0
nQG0
ING1
nING1
0
QH
nQH
1
QG1
nQG1
1
SEL_QH MODE_QGx
ICS854S54AYI-08 FEBRUARY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS854S54I-08 Data Sheet
OCTAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 1. Pin Descriptions
Number
1, 2
4, 5
3, 14, 26, 35, 46, 55
6, 11, 23, 38, 43, 58
7, 8
9, 10
12, 13
15, 16
17
18
19, 21
20, 22
24, 25
27, 29
28, 30
31
32
33, 34
36, 37
39, 40
41, 42
44, 45
47, 48
49
50
51, 53
52, 54
56
57
59, 61
60, 62
63
64
Name
QA0, nQA0
QA1, nQA1
GND
V
DD
QB, nQB
nQF, QF
nQE1, QE1
nQE0, QE0
nINF
INF
nINE1, nINE0
INE1, INE0
ADR1, ADR0
ING0, ING1
nING0, nING1
INH
nINH
QG0, nQG0
QG1, nQG1
QH, nQH
nQD, QD
nQC1, QC1
nQC0, QC0
nIND
IND
nINC1, nINC0
INC1, INC0
SCLK
SDA
INA0, INA1
nINA0, nINA1
INB
nINB
Output
Power
Power
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Differential output pair. LVDS interface levels.
Power supply ground.
Power supply pins.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Inverting differential LVPECL clock input. V
DD
/2 default when left
floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
DD
/2 default when left
floating.
Non-inverting differential LVPECL clock input.
Serial address select pins. LVCMOS / LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
DD
/2 default when left
floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
DD
/2 default when left
floating.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Inverting differential LVPECL clock input. V
DD
/2 default when left
floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
DD
/2 default when left
floating.
Non-inverting differential LVPECL clock input.
I
2
C Serial address select pin. LVCMOS/LVTTL interface levels.
I
2
C Shift register serial input. Data sampled on the rising edge of
SCLK. LVCMOS/LVTTL interface levels.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
DD
/2 default when left
floating.
Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input. V
DD
/2 default when left
floating.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
ICS854S54AYI-08 FEBRUARY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS854S54I-08 Data Sheet
OCTAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
50
50
50
Maximum
Units
k
Ω
k
Ω
k
Ω
R
PULLDOWN
Input Pulldown Resistor
R
PULLUP
R
VDD/2
Input Pullup Resistor
Pullup/Pulldown Resistors
Function Tables
Table 3A. Internal Control Input Function Table, SEL_QB, MODE_QAx
I
2
C Bits
SEL_QB
0
1
X
MODE_QAx
1
1
0
QB, nQB
Follows INA0, nINA0 input
Follows INA1, nINA1 input
High-Impedance
Outputs
QA0, nQA0
Follows INB, nINB input
Follows INB, nINB input
Follows INA1, nINA1 input
QA1, nQA1
Follows INB, nINB input
Follows INB, nINB input
Follows INA0, nINA0 input
Table 3B. Internal Control Input Function Table, SEL_QD, MODE_QCx
I
2
C Bits
SEL_QD
0
1
X
MODE_QCx
1
1
0
QB, nQB
Follows INC0, nINC0 input
Follows INC1, nINC1 input
High-Impedance
Outputs
QA0, nQA0
Follows IND, nIND input
Follows IND, nIND input
Follows INC1, nINC1 input
QA1, nQA1
Follows IND, nIND input
Follows IND, nIND input
Follows INC0, nINC0 input
Table 3C. Internal Control Input Function Table, SEL_QF, MODE_QEx
I
2
C Bits
SEL_QF
0
1
X
MODE_QEx
1
1
0
QB, nQB
Follows INE0, nINE0 input
Follows INE1, nINE1 input
High-Impedance
Outputs
QA0, nQA0
Follows INF, nINF input
Follows INF, nINF input
Follows INE1, nINE1 input
QA1, nQA1
Follows INF, nINF input
Follows INF, nINF input
Follows INE0, nINE0 input
Table 3D. Internal Control Input Function Table, SEL_QH, MODE_QGx
I
2
C Bits
SEL_QH
0
1
X
MODE_QGx
1
1
0
QB, nQB
Follows ING0, nING0 input
Follows ING1, nING1 input
High-Impedance
Outputs
QA0, nQA0
Follows INH, nINH input
Follows INH, nINH input
Follows ING1, nING1 input
QA1, nQA1
Follows INH, nINH input
Follows INH, nINH input
Follows ING0, nING0 input
ICS854S54AYI-08 FEBRUARY 4, 2010
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©2010 Integrated Device Technology, Inc.
ICS854S54I-08 Data Sheet
OCTAL 2:1 AND 1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER
I
2
C Control Description
The ICS854S54I-08 uses an industry standard I
2
C interface to control
the direction of the 4 separate 2:1, 1:2 mux switch blocks. Each
individual block is controlled by two bits of the 8 bit Data Byte. The
Data Byte bit pairs are summarized as follows:
Control Signals
Bit Pair 1
– INA0/nINA0, INA1/nINA1, INB/nINB, QB/nQB
SEL_QB:MODE_QAx
Bit Pair 2
– INC0/nINC0, INC1/nINC1, IND/nIND, QD/nQD
SEL_QD:MODE_QCx
Bit Pair 3
– INE0/nINE0, INE1/nINE1, INF/nINF, QF/nQF
SEL_QF:MODE_QEx
Bit Pair 4
– ING0/nING0, ING1/nING1, INH/nINH, QH/nQH
SEL_QH:MODE_QGx
Data Byte 0
Bit 7
Control Bit
Power-up
Default Value
MODE_QGx
1
Bit 6
SEL_QH
0
Bit 5
MODE_QEx
1
Bit 4
SEL_QF
0
Bit 3
MODE_QCx
1
Bit 2
SEL_QD
0
Bit 1
MODE_QAx
1
Bit 0
SEL_QB
0
I
2
C Addressing
The ICS854S54I-08 can be set to decode one of four addresses to
minimize the chance of address conflict on the I
2
C bus. The address
that is decoded is controlled by the setting of the ADR_1, ADR_0
(pins 24 and 25).
ADR_SEL (pins 24 & 25) = Default (1, 1)
Bit 7
1
Bit 6
1
Bit 5
0
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1
1
Bit 0
R/W
ADR_SEL (pins 24 & 25) = Default (1, 0)
Bit 7
1
Bit 6
1
Bit 5
0
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1
0
Bit 0
R/W
ADR_SEL (pins 24 & 25) = Default (0, 1)
Bit 7
1
Bit 6
1
Bit 5
0
Bit 4
1
Bit 3
1
Bit 2
0
Bit 1
1
Bit 0
R/W
ADR_SEL (pins 24 & 25) = Default (0, 0)
Bit 7
1
Bit 6
1
Bit 5
0
Bit 4
1
Bit 3
1
Bit 2
0
Bit 1
0
Bit 0
R/W
ICS854S54AYI-08 FEBRUARY 4, 2010
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©2010 Integrated Device Technology, Inc.
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