Low Skew, 1-to-8, Differential-to-0.7V
HCSL Clock Distribution Chip
General Description
The 85108 is a low skew, high performance 1-to-8
Differential-to-0.7V HCSL Clock Distribution Chip. The 85108 CLK,
nCLK pair can accept most differential input levels and translates
them to 3.3V HCSL output levels. The 85108 provides a low power,
low noise, low skew, point-to-point solution for distributing HCSL
clock signals.
Guaranteed output and part-to-part skew specifications make the
85108 ideal for those applications demanding well defined
performance and repeatability.
85108
DATA SHEET
Features
•
•
•
•
•
•
•
•
•
•
Eight 0.7V differential HCSL clock output pairs
CLK/nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 500MHz
Additive phase jitter, RMS: 0.09ps (typical)
Output skew: 80ps (maximum)
Part-to-part skew: 400ps (maximum)
Propagation delay: 3ns (maximum)
Full 3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
Q0
nQ0
Q1
nQ1
Q2
nQ2
CLK
Pulldown
nCLK
Pullup/Pulldown
IREF
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Pin Assignment
Q0
nQ0
V
DD
CLK
nCLK
Q1
nQ1
Q2
nQ2
IREF
Q3
nQ3
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q7
nQ7
GND
V
DD
Q6
nQ6
Q5
nQ5
V
DD
GND
Q4
nQ4
85108
24-Lead TSSOP, 173-MIL
4.4mm x 7.8mm x 0.925mm package body
G Package
Top View
85108 Rev A 6/11/15
1
©2015 Integrated Device Technology, Inc.
85108 DATA SHEET
Table 1. Pin Descriptions
Number
1, 2
3, 16, 21
4
5
6, 7
8, 9
10
11, 12
13, 14
15, 22
17, 18
19, 20
23, 24
Name
Q0, nQ0
V
DD
CLK
nCLK
Q1, nQ1
Q2, nQ2
IREF
Q3, nQ3
nQ4, Q4
GND
nQ5, Q5
nQ6, Q6
nQ7, Q7
Output
Output
Power
Output
Output
Output
Output
Power
Input
Input
Output
Output
Pulldown
Pullup/
Pulldown
Type
Description
Differential output pair. HCSL interface levels.
Power supply pins.
Non-inverting differential clock input.
Inverting differential clock input.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
External fixed precision resistor (475
) from this pin to ground provides a reference
current used for differential current-mode Qx/nQx clock outputs.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Power supply ground.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistors
Input Pulldown Resistors
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
k
k
Function Tables
Table 3. Clock Input Function Table
Inputs
CLK
0
1
0
1
Biased; NOTE 1
Biased; NOTE 1
nCLK
1
0
Biased; NOTE 1
Biased; NOTE 1
0
1
Q[0:7]
LOW
HIGH
LOW
HIGH
HIGH
LOW
Outputs
n[0:7]
HIGH
LOW
HIGH
LOW
LOW
HIGH
Input to Output Mode
Differential to Differential
Differential to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Polarity
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
NOTE 1: Please refer to the Application Information section
Wiring the Differential Input to Accept Single Ended Levels.
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-0.7V HCSL CLOCK
DISTRIBUTION CHIP
2
Rev A 6/11/15
85108 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
87.8C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
V
DD
I
DD
Parameter
Power Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.97
Typical
3.3
Maximum
3.63
27
Units
V
mA
Table 4B. Differential DC Characteristics,
V
DD
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
PP
V
CMR
Parameter
Input High Current
Input Low Current
nCLK
Peak-to-Peak Voltage; NOTE 1
Common Mode Input Voltage; NOTE 1, 2
CLK, nCLK
CLK
Test Conditions
V
DD
= V
IN
= 3.63V
V
DD
= 3.63V, V
IN
= 0V
V
DD
= 3.635V, V
IN
= 0V
-5
-150
0.15
GND + 0.5
1.3
V
DD
– 0.85
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
NOTE 1: V
IL
should not be less than -0.3V.
NOTE 2: Common mode input voltage is defined as V
IH
.
Rev A 6/11/15
3
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-0.7V HCSL CLOCK
DISTRIBUTION CHIP
85108 DATA SHEET
AC Electrical Characteristics
Table 5. HCSL AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 10%, T
A
= -40°C to 85°C
Symbol
f
MAX
t
PD
tsk(o)
tsk(pp)
tjit
Parameter
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
Ring-back Voltage Margin;
NOTE 5, 6
Time before V
RB
is allowed;
NOTE 5, 6
Absolute Maximum Output
Voltage; NOTE 7, 8
Absolute Minimum Output
Voltage; NOTE 7, 9
Absolute Crossing Voltage;
NOTE 7, 10, 11
Total Variation of V
CROSS
over
all edges; NOTE 7, 10, 12
Rise/Fall Edge Rate;
NOTE 5, 13
odc
Output Duty Cycle; NOTE 14
Measured between -150mV to +150mV
0.6
45
-300
250
550
140
5.5
55
250MHz, Integration Range:
12kHz – 20MHz
-100
500
1150
0.09
1.5
Test Conditions
Minimum
Typical
Maximum
500
3
80
400
Units
MHz
ns
ps
ps
ps
V
RB
t
STABLE
V
MAX
V
MIN
V
CROSS
V
CROSS
100
mV
ps
mV
mV
mV
mV
V/ns
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: All parameters measured at ƒ
250MHz unless noted otherwise.
NOTE 1: Measured from the differential input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.
NOTE 5: Measurement taken from differential waveform.
NOTE 6: T
STABLE
is the time the differential clock must maintain a minimum ±150mV differential voltage after rising/falling edges before it is
allowed to drop back into the V
RB
±100mV differential range. See Parameter Measurement Information Section.
NOTE 7: Measurement taken from single-ended waveform.
NOTE 8: Defined as the maximum instantaneous voltage including overshoot. See Parameter Measurement Information Section.
NOTE 9: Defined as the minimum instantaneous voltage including undershoot. See Parameter Measurement Information Section.
NOTE 10: Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 11: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 12: Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the
V
CROSS
for any particular system. See Parameter Measurement Information Section.
NOTE 13: Measured from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 14: Input duty cycle must be 50%.
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-0.7V HCSL CLOCK
DISTRIBUTION CHIP
4
Rev A 6/11/15
85108 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 250MHz
12kHz to 20MHz = 0.09ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements hase
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Rev A 6/11/15
5
LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-0.7V HCSL CLOCK
DISTRIBUTION CHIP
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