HIGH-SPEED 3.3V
IDT70V659/58/57S
128/64/32K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
Features
◆
◆
◆
◆
◆
◆
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12/15ns (max.)
Dual chip enables allow for depth expansion without
external logic
IDT70V659/58/57 easily expands data bus width to 72 bits
or more using the Master/Slave select when cascading
more than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
◆
◆
◆
◆
◆
◆
◆
◆
◆
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Supports JTAG features compliant to IEEE 1149.1
LVTTL-compatible, single 3.3V (±150mV) power supply for
core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 208-pin Plastic Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
BE
3R
BE
2R
BE
1R
BE
0R
Functional Block Diagram
BE
3L
BE
2L
BE
1L
BE
0L
R/
W
L
CE
0L
CE
1L
B
E
0
L
B
E
1
L
B
E
2
L
B
E
3
L
BBBB
EEEE
3 2 10
RRRR
R/
W
R
CE
0R
CE
1R
OE
L
Dout0-8_L
Dout0-8_R
Dout9-17_L
Dout9-17_R
Dout18-26_L Dout18-26_R
Dout27-35_L Dout27-35_R
OE
R
128/64/32K x 36
MEMORY
ARRAY
I/O
0L-
I/O
35L
Di n_L
Di n_R
I/O
0R -
I/O
35R
A
16 L(1)
A
0L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A
16R(1)
A
0R
CE
0L
CE
1L
OE
L
R/W
L
BUSY
L(2,3)
SEM
L
INT
L(3)
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OE
R
R/W
R
CE
0R
CE
1R
M/S
BUSY
R(2,3)
SEM
R
INT
R(3)
TDI
TDO
JTAG
TMS
TCK
TRST
4869 drw 01
NOTES:
1. A
16
is a NC for IDT70V658. Also, Addresses A
16
and A
15
are NC's for IDT70V657.
2.
BUSY
is an input as a Slave (M/S=V
IL
) and an output when it is a Master (M/S=V
IH
).
3.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
OCTOBER 2008
DSC-4869/7
1
©2008 Integrated Device Technology, Inc.
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT70V659/58/57 is a high-speed 128/64/32K x 36 Asynchro-
nous Dual-Port Static RAM. The IDT70V659/58/57 is designed to be used
as a stand-alone 4/2/1Mbit Dual-Port RAM or as a combination MASTER/
SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory
system applications results in full-speed, error-free operation without the
need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (either
CE
0
or CE
1
) permit the
on-chip circuitry of each port to enter a very low standby power mode.
The 70V659/58/57 can support an operating voltage of either 3.3V
or 2.5V on one or both ports, controlled by the OPT pins. The power supply
for the core of the device (V
DD
) remains at 3.3V.
2
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations
(3,4,5,6,7,8)
03/19/04
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
V
SS
V
DDQR
I/O
18R
I/O
18L
V
SS
V
DD
TDI
TDO
NC
NC
NC
A
16L(1)
A
15L(2)
A
14L
A
13L
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
BE
3L
BE
2L
BE
1L
BE
0L
CE
1L
CE
0L
V
DD
V
DD
V
SS
V
SS
SEM
L
OE
L
R/W
L
BUSY
L
INT
L
NC
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
V
DD
V
DD
V
SS
OPT
L
I/O
17L
I/O
17R
V
DDQR
V
SS
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
I/O
19L
I/O
19R
I/O
20L
I/O
20R
V
DDQL
V
SS
I/O
21L
I/O
21R
I/O
22L
I/O
22R
V
DDQR
V
SS
I/O
23L
I/O
23R
I/O
24L
I/O
24R
V
DDQL
V
SS
I/O
25L
I/O
25R
I/O
26L
I/O
26R
V
DDQR
V
SS
V
DD
V
DD
V
SS
V
SS
V
DDQL
V
SS
I/O
27R
I/O
27L
I/O
28R
I/O
28L
V
DDQR
V
SS
I/O
29R
I/O
29L
I/O
30R
I/O
30L
V
DDQL
V
SS
I/O
31R
I/O
31L
I/O
32R
I/O
32L
V
DDQR
V
SS
I/O
33R
I/O
33L
I/O
34R
I/O
34L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
70V659/58/57DR
DR-208
(7)
208-Pin PQFP
Top View
(8)
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
I/O
16L
I/O
16R
I/O
15L
I/O
15R
V
SS
V
DDQL
I/O
14L
I/O
14R
I/O
13L
I/O
13R
V
SS
V
DDQR
I/O
12L
I/O
12R
I/O
11L
I/O
11R
V
SS
V
DDQL
I/O
10L
I/O
10R
I/O
9L
I/O
9R
V
SS
V
DDQR
V
DD
V
DD
V
SS
V
SS
V
SS
V
DDQL
I/O
8R
I/O
8L
I/O
7R
I/O
7L
V
SS
V
DDQR
I/O
6R
I/O
6L
I/O
5R
I/O
5L
V
SS
V
DDQL
I/O
4R
I/O
4L
I/O
3R
I/O
3L
V
SS
V
DDQR
I/O
2R
I/O
2L
I/O
1R
I/O
1L
4869 drw 02a
NOTES:
1. Pin is a NC for IDT70V658 and IDT70V657.
2. Pin is a NC for IDT70V657.
3. All V
DD
pins must be connected to 3.3V power supply.
4. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
DD
(3.3V) and 2.5V if OPT pin for that port is
set to V
SS
(0V).
5. All V
SS
pins must be connected to ground.
6. Package body is approximately 28mm x 28mm x 3.5mm.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
V
SS
V
DDQL
I/O
35R
I/O
35L
V
DD
TMS
TCK
TRST
NC
NC
NC
A
16R(1)
A
15R(2)
A
14R
A
13R
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
BE
3R
BE
2R
BE
1R
BE
0R
CE
1R
CE
0R
V
DD
V
DD
V
SS
V
SS
SEM
R
OE
R
R/W
R
BUSY
R
INT
R
M/S
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
V
DD
V
SS
V
SS
OPT
R
I/O
0L
I/O
0R
V
DDQL
V
SS
3
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
,5,6,7,8)
,5,6,7,8
Pin Configurations
(3,4,5,6,7,8
(con't.)
70V659/58/57BC
BC-256
(7)
256-Pin BGA
Top View
(8)
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
03/19/04
A1
NC
B1
TDI
B2
NC
B3
NC
B4
A
14L
B5
A
11L
B6
A
8L
B7
BE
2L
B8
CE
1L
B9
OE
L
B10
INT
L
B11
A
5L
B12
A
2L
B13
A
0L
B14
NC
B15
NC
B16
I/O
18L
C1
NC
C2
TDO
C3
NC
C4
A
15L(2)
A
12L
C5
C6
A
9L
C7
BE
3L
C8
CE
0L
R/W
L
C9
C10
NC
C11
A
4L
C12
A
1L
C13
NC
C14
I/O
17L
C15
NC
C16
I/O
18R
I/O
19L
D1
D2
V
SS
D3
A
16L(1)
D4
A
13L
D5
A
10L
D6
A
7L
D7
BE
1L
BE
0L
SEM
L
BUSY
L
D8
D9
D10
D11
A
6L
D12
A
3L
D13
OPT
L
I/O
17R
I/O
16L
D14
D15
D16
I/O
20R
I/O
19R
I/O
20L
E1
E2
E3
V
DD
E4
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
V
DDQR
V
DDQR
V
DD
I/O
15R
I/O
15L
I/O
16R
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
I/O
21R
I/O
21L
I/O
22L
V
DDQL
V
DD
F1
F2
F3
F4
F5
V
DD
F6
V
SS
F7
V
SS
F8
V
SS
F9
V
SS
F10
V
DD
F11
V
DD
V
DDQR
I/O
13L
I/O
14L
I/O
14R
F12
F13
F14
F15
F16
I/O
23L
I/O
22R
I/O
23R
V
DDQL
V
DD
G1
G2
G3
G4
G5
V
SS
G6
V
SS
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
DD
V
DDQR
I/O
12R
I/O
13R
I/O
12L
G12
G13
G14
G15
G16
I/O
24R
I/O
24L
I/O
25L
V
DDQR
V
SS
H1
H2
H3
H4
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
DDQL
I/O
10L
I/O
11L
I/O
11R
H13
H14
H15
H16
I/O
26L
I/O
25R
J1
J2
I/O
26R
V
DDQR
V
SS
J3
J4
J5
V
SS
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
V
DDQL
I/O
9R
J13
J14
IO
9L
I/O
10R
J15
J16
I/O
27L
I/O
28R
I/O
27R
V
DDQL
K1
K2
K3
K4
V
SS
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
K9
V
SS
K10
V
SS
K11
V
SS
V
DDQR
I/O
8R
I/O
7R
I/O
8L
K12
K13
K14
K15
K16
I/O
29R
L1
I/O
29L
I/O
28L
V
DDQL
V
SS
L2
L3
L4
L5
V
SS
L6
V
SS
L7
V
SS
L8
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
DDQR
I/O
6R
I/O
6L
I/O
7L
L13
L14
L15
L16
I/O
30L
I/O
31R
I/O
30R
V
DDQR
V
DD
M1
M2
M3
M4
M5
V
SS
M6
V
SS
M7
V
SS
M8
V
SS
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DDQL
I/O
5L
M13
M14
I/O
4R
I/O
5R
M15
M16
I/O
32R
I/O
32L
I/O
31L
V
DDQR
N1
N2
N3
N4
V
DD
N5
V
DD
N6
V
SS
N7
V
SS
N8
V
SS
N9
V
SS
N10
V
DD
N11
V
DD
V
DDQL
I/O
3R
I/O
3L
I/O
4L
N12
N13
N14
N15
N16
I/O
33L
I/O
34R
I/O
33R
V
DD
P1
P2
P3
P4
V
DDQR
V
DDQR
V
DDQL
P5
P6
P7
V
DDQL
V
DDQR
V
DDQR
V
DDQL
V
DDQL
P8
P9
P10
P11
P12
V
DD
P13
I/O
2L
P14
I/O
1R
I/O
2R
P15
P16
I/O
35R
I/O
34L
TMS A
16R(1)
A
13R
R1
R2
R3
R4
R5
A
10R
R6
A
7R
R7
BE
1R
BE
0R
SEM
R
BUSY
R
R8
R9
R10
R11
A
6R
R12
A
3R
R13
I/O
0L
I/O
0R
R14
R15
I/O
1L
R16
I/O
35L
T1
NC
T2
TRST
T3
NC
T4
A
15R(2)
T5
A
12R
T6
A
9R
T7
BE
3R
CE
0R
R/W
R
T8
T9
T10
M/S
T11
A
4R
T12
A
1R
T13
OPT
R
T14
NC
T15
NC
T16
,
NC
TCK
NC
NC
A
14R
A
11R
A
8R
BE
2R
CE
1R
OE
R
INT
R
A
5R
A
2R
A
0R
NC
NC
4869 drw 02c
,
NOTES:
1. Pin is a NC for IDT70V658 and IDT70V657.
2. Pin is a NC for IDT70V657.
3. All V
DD
pins must be connected to 3.3V power supply.
4. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
DD
(3.3V), and 2.5V if OPT pin for that port is
set to V
SS
(0V).
5. All V
SS
pins must be connected to ground supply.
6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
4
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
(3,4,5,6,7,8)
(con't.)
03/19/04
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
I/O
19L
2
I/O
18L
3
V
SS
4
TDO
5
NC
6
A
16L(1)
7
A
12L
8
A
8L
9
BE
1L
10 11
V
DD
12
INT
L
13 14
A4
L
A
0L
15
OPT
L
16 17
I/O
17L
V
SS
SEM
L
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
I/O
20R
V
S S
I/O
18R
TDI
NC
A
13L
A
9L
BE
2L
CE
0L
V
SS
BUSY
L
A5
L
A
1L
V
SS
V
DDQR
I/O16L
I/O
15R
V
DDQL
I/O
19R
V
DDQR
V
DD
NC
A
14L
A
10L
BE
3L
CE
1L
V
SS
R/
W
L
A6
L
A
2L
V
DD
I/O
16R
I/O
15L
V
SS
I/O
22L
V
SS
I/O
21L
I/O
20L
A
15L (2)
A
11L
A
7L
BE
0L
V
DD
OE
L
NC
A
3
L
V
DD
I/O
17R
V
DDQL
I/O
14L
I/O
14R
I/O
23L
I/O
22R
V
DDQR
I/O
21R
I/O
12L
I/O
13R
V
SS
I/O
13L
V
DDQL
I/O
23R
I/O
24L
V
SS
V
SS
I/O
12R
I/O
11L
V
DDQR
I/O
26L
V
SS
I/O
25L
I/O
24R
I/O
9L
V
DDQL
I/O
10L
I/O
11R
V
DD
I/O
26R
V
DDQR
I/O
25R
70V659/58/57BF
BF-208
(7)
208-Ball BGA
Top View
(8)
V
DD
I/O
9R
V
SS
I/O
10R
V
DDQL
V
DD
V
SS
V
SS
V
S S
V
DD
V
SS
V
DDQR
I/O
28R
V
SS
I/O
2 7R
V
S S
I/O
7R
V
DDQL
I/O8R
V
SS
I/O
29R
I/O
28L
V
DDQR
I/O
27L
I/O
6R
I/O
7L
V
SS
I/O
8L
V
DDQL
I/O
29L
I/O
30R
V
SS
V
SS
I/O
6L
I/O
5R
V
DDQR
I/O
31L
V
S S
I/O
31R
I/O
30L
I/O
3R
V
D DQL
I/O
4R
I/O
5L
I/O
32R
I/O
32L
V
DDQR
I/O
35R
TRST
A
16R (1 )
A
12R
A
8R
BE
1R
V
DD
SEM
R
INT
R
A
4R
I/O
2L
I/O
3L
V
SS
I/O
4L
V
SS
I/O
33L
I/O
34 R
TCK
NC
A
13R
A
9R
BE
2R
CE
0
R
V
S S
BUSY
R
R/
W
R
A
5R
A
1R
V
SS
V
DDQL
I/O
1R
V
DDQR
I/O
33R
I/O
34L
V
DDQL
TMS
NC
A
14R
A
10R
BE
3R
CE
1R
V
SS
A
6R
A
2R
V
S S
I/O
0R
V
S S
I/O
2R
V
S S
I/O
35L
V
DD
NC
A
15R (2)
A
11R
A
7R
BE
0R
V
DD
OE
R
M/
S
A
3R
A
0R
V
DD
OPT
R
I/O
0L
I/O
1L
4869 drw 02b
NOTES:
1. Pin is a NC for IDT70V658 and IDT70V657.
2. Pin is a NC for IDT70V657.
3. All V
DD
pins must be connected to 3.3V power supply.
4. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
DD
(3.3V) and 2.5V if OPT pin for that port is
set to V
SS
(0V).
5. All V
SS
pins must be connected to ground.
6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
5
FPGA/CPLD
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