power amplifier module intended for use in PCS handsets and
wireless local loop subscriber units. The amplifier meets the
requirements of PCS-1900 or IS-98 (CDMA) systems. It is a
member of Celeritek’s new
True
v
Triangle
™
family of 3V
power amplifier modules.
1.85 to 1.91 GHz
3.2V, 28 dBm, PCS
50 Ohm Linear Power Module
Functional Block Diagram
GND GND
12
11
RF IN
1
GND
10
6
Vgg
5
GND
4
RF OUT
7
8
9
GND GND GND
Vdd1
2
Vdd2/3
3
Backside is Ground
The CPM1530-PM is packaged in a low-cost, space
efficient, matched module that provides excellent electrical
stability and low thermal resistance. The part requires no
external matching and a fixed negative voltage significantly
reducing space and cost and enhancing ease of use.
This device is unconditionally stable under all source
and load impedances.
Absolute Maximum Ratings
Parameter
Rating
Parameter
Rating
Parameter
Rating
Drain Voltage (+Vd)
Drain Current (Id)
RF Input Power
DC Gate Voltage (-Vg)
+5.5 V*
1.8 A
3 dBm*
-3.0 V*
Power Dissipation
Thermal Resistance
Storage Temperature
5W
20°C/W
-65°C to +150°C
Operating Temperature
Channel Temperature
Soldering Temperature
-40°C to +90°C
150°C
260°C for 5 Sec.
* Max (+Vd) and (-Vg) under linear operation. Max potential difference across the device at 1dB gain compression point (2Vd + |-Vg|) not to exceed the minimum breakdown voltage (Vbr) of +12V.
Recommended Operating Conditions
Parameter
Typ
Units
Parameter
Typ
Units
Drain Voltage (+Vd)
Gate Voltage (Vgg) (Fixed and regulated)
3.2 to 4.1
-2.5
Volts
Volts
Operating Temperature (PC Board)
-30 to +80
°C
Application Information
The CPM1530-PM is a three stage amplifier that requires
positive and negative supply voltages for proper operation. It
is essential when turning on the device that the negative sup-
ply be applied before the positive supply. When turning the
device off, the positive supply should be removed before the
negative supply is removed.
The CPM1530-PM can be operated over a range of sup-
ply voltages and bias points. It is important that the maximum
power dissipation of the package be observed at all times and
that the maximum voltage across the device is not exceeded.
accomplished via a fixed -2.5 V to pin 6. The positive supply
voltages are applied to pins 2 and 3. Bypass decoupling is pro-
vided on-board.
The recommended DC by-pass capacitance and low-pass
in-line inductance are shown in the evaluation board on Page 4.
Inadequate by-pass capacitance and inductance around the
DC supply lines can compromise the adjacent channel power
ratio (ACPR), reduce power gain and/or create oscillations.
Supply Ramping
To obtain power ramping, gate supply con-
trol is recommended.
Mode Switching
If further efficiency is required at lower
power levels, then an adjustment of the fixed Vgg can be made.
– Continued on Page 2 –
Circuit Design Considerations
Biasing
A negative gate voltage is necessary to set the bias
currents of the three FET stages in the CPM1530-PM. This is
3236 Scott Boulevard
Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
CPM1530-PM
Electrical Characteristics
Advanced Product Information - August 1999
(2 of 4)
Unless otherwise specified, the following specifications are guaranteed at room temperature with drain voltage (+Vd) = 3.7 V.
Parameter
Condition
Min
Typ
Max
Units
Frequency Range
Gain
Gain Ripple*
Gain Variation
Power Output
Harmonics
Noise Power in Receive Band
Linearity (ACPR)
Spurious Signal
Noise Figure
Input Return Loss
Efficiency (Vdd = 3.2 V)
@ Digital power output
1850-1910 MHz
Over supply voltage
Over temperature
Meets IS-98 CDMA mask
2nd @ Digital power output, no output trapping, Po=+28.0 dBm
3rd @ Digital power output, no output trapping, Po=+28.0 dBm
30 kHz bandwidth
CDMA modulation @ +28.0 dBm Pout, 1.25 MHz offset
VSWR = 3:1 in-band, VSWR = 10:1 out-of-band
1.85
28
1.91
30
1.5
2
0.03
+28
-30
-40
-94
-45
-80
3.0
10
7
35
470
130
1.1
-2.5
Pout = +16.0 dBm - CDMA
Pout = +28.0 dBm - CDMA
Positive Supply Current (Id)
Pout IS-98 CDMA (27 dBm)
Quiescent Current (Iq)
No RF CDMA mode
Negative Supply Current (-Ig)
Includes internal resistor divider
Negative Supply Voltage (-Vgg) Fixed and regulated
* Specifications guaranteed over the temperature range of -20°C to +80°C
5
32
2.0
GHz
dB
dB
dB/V
dB/°C
dBm
dBc
dBc
dBm
dBc/30KHz
dBc
dB
dB
%
%
mA
mA
mA
V
– Continued from Page 1 –
Modulation
When biased as specified, the CPM1530-PM
will achieve the required adjacent channel response for the
digital PCS system specified. Celeritek tests each product
under digital modulation to ensure correlation to customer
applications.
Thermal
1. The ground pad on the backside of the CPM1530-PM must
be soldered to the ground plane.
2. All 12 leads of the package must be soldered to the appro-
priate electrical connection.
3236 Scott Boulevard, Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
CPM1530-PM
Advanced Product Information - August 1999
Recommended Application Circuit
Note: This schematic represents the topology of the application circuit recommended by Celeritek.
(3 of 4)
Evaluation Board Schematic
12
1
RF IN
Vdd
0.1 µF
3
10 µF
0.1 µF
7
8
11
10
6
Vgg
0.1 µF
Board substrate:
ER = 4.60
Thickness = 0.031 in.
2
CPM1530-PM
5
4
RF OUT
9
Physical Dimensions
Ordering Information
The CPM1530-PM is available in a surface mount 50 ohm matched module and devices are available in tube or tape and reel.
Part Number for Ordering
Package
CPM1530-PM-00S0
PM-12 CDMA surface mount power package in tube
CPM1530-PM-00ST
PM-12 CDMA surface mount power package in tape and reel
PB-CPM1530-PM-00S0
Evaluation Board with SMA connectors for CPM1530-PM-00S0 tested CDMA
3236 Scott Boulevard
Santa Clara, California 95054
Phone: (408) 986-5060
Fax: (408) 986-5095
CPM1530-PM
Notes
Advanced Product Information - August 1999
(4 of 4)
Celeritek reserves the right to make changes without further notice to any products herein. Celeritek makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Celeritek assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating
parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Celeritek does not convey any license under its patent
rights nor the rights of others. Celeritek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the Celeritek product could create a situation where personal
injury or death may occur. Should Buyer purchase or use Celeritek products for any such unintended or unauthorized application, Buyer shall indemnify and hold Celeritek
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out
of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Celeritek was negligent
regarding the design or manufacture of the part. Celeritek is a registered trademark of Celeritek, Inc. Celeritek, Inc. is an Equal Opportunity/Affirmative Action Employer.
3236 Scott Boulevard, Santa Clara, California 95054
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
