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H8/3045: 产品描述Hitachi Single-Chip Microcomputer; 文件大小2MB，共867页; 制造商Hitachi （Renesas ）; 官网地址http://www.renesas.com/eng/

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H8/3045概述

Hitachi Single-Chip Microcomputer

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Hitachi Single-Chip Microcomputer

H8/3048 Series

H8/3048

HD64F3048, HD6473048, HD6433048

H8/3047

HD6433047

H8/3045

HD6433045

H8/3044

HD6433044

Hardware Manual

ADE-602-073B

Preface

The H8/3048 Series is a series of high-performance microcontrollers that integrate system

supporting functions together with an H8/300H CPU core.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a

concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address

space.

The on-chip supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a

programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication

interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller

(DMAC), a refresh controller, and other facilities. Of the two SCI channels, one has been

expanded to support the ISO/IEC7816-3 smart card interface. Functions have also been added to

reduce power consumption in battery-powered applications: individual modules can be placed in

standby, and the frequency of the system clock supplied to the chip can be divided down under

software control.

The address space is divided into eight areas. The data bus width and access cycle length can be

selected independently in each area, simplifying the connection of different types of memory.

Seven operating modes (modes 1 to 7) are provided, offering a choice of data bus width and

address space size.

With these features, the H8/3048 Series can be used to implement compact, high-performance

systems easily.

In addition to its masked-ROM versions, the H8/3048 Series has a ZTAT™*

version with user-

programmable on-chip PROM and an F-ZTAT™*

version with on-chip flash memory that can be

programmed on-board. These versions enable users to respond quickly and flexibly to changing

application specifications.

This manual describes the H8/3048 Series hardware. For details of the instruction set, refer to the

H8/300H Series Programming Manual.

Notes: 1. ZTAT™ (Zero Turn-Around-time) is a trademark of Hitachi, Ltd.

2. F-ZTAT™ (Flexible ZTAT) is a trademark of Hitachi, Ltd.

Contents

Section 1

1.1

1.2

1.3

Overview

......................................................................................................

Overview.........................................................................................................................

Block Diagram................................................................................................................

Pin Description ...............................................................................................................

1.3.1

Pin Arrangement.............................................................................................

1.3.2

Pin Assignments in Each Mode......................................................................

1.3.3

Pin Functions ..................................................................................................

Section 2

2.1

CPU

............................................................................................................... 15

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Overview.........................................................................................................................

2.1.1

Features...........................................................................................................

2.1.2

Differences from H8/300 CPU .......................................................................

CPU Operating Modes....................................................................................................

Address Space.................................................................................................................

Register Configuration....................................................................................................

2.4.1

Overview.........................................................................................................

2.4.2

General Registers............................................................................................

2.4.3

Control Registers ............................................................................................

2.4.4

Initial CPU Register Values ............................................................................

Data Formats...................................................................................................................

2.5.1

General Register Data Formats.......................................................................

2.5.2

Memory Data Formats ....................................................................................

Instruction Set.................................................................................................................

2.6.1

Instruction Set Overview ................................................................................

2.6.2

Instructions and Addressing Modes................................................................

2.6.3

Tables of Instructions Classified by Function.................................................

2.6.4

Basic Instruction Formats ...............................................................................

2.6.5

Notes on Use of Bit Manipulation Instructions ..............................................

Addressing Modes and Effective Address Calculation ..................................................

2.7.1

Addressing Modes ..........................................................................................

2.7.2

Effective Address Calculation ........................................................................

Processing States ............................................................................................................

2.8.1

Overview.........................................................................................................

2.8.2

Program Execution State ................................................................................

2.8.3

Exception-Handling State...............................................................................

2.8.4

Exception-Handling Sequences ......................................................................

2.8.5

Bus-Released State .........................................................................................

2.8.6

Reset State ......................................................................................................

2.8.7

Power-Down State ..........................................................................................

2.9

Basic Operational Timing...............................................................................................

2.9.1

Overview.........................................................................................................

2.9.2

On-Chip Memory Access Timing...................................................................

2.9.3

On-Chip Supporting Module Access Timing .................................................

2.9.4

Access to External Address Space..................................................................

Section 3

3.1

MCU Operating Modes

........................................................................... 55

3.2

3.3

3.4

3.5

3.6

Overview.........................................................................................................................

3.1.1

Operating Mode Selection ..............................................................................

3.1.2

Mode Control Register (MDCR) ....................................................................................

System Control Register (SYSCR).................................................................................

Operating Mode Descriptions.........................................................................................

3.4.1

Mode 1 ............................................................................................................

3.4.2

Mode 2 ............................................................................................................

3.4.3

Mode 3 ............................................................................................................

3.4.4

Mode 4 ............................................................................................................

3.4.5

Mode 5 ............................................................................................................

3.4.6

Mode 6 ...........................................................................................................

3.4.7

Mode 7 ...........................................................................................................

Pin Functions in Each Operating Mode..........................................................................

Memory Map in Each Operating Mode..........................................................................

Section 4

4.1

Exception Handling

.................................................................................. 71

4.2

4.3

4.4

4.5

4.6

Overview.........................................................................................................................

4.1.1

Exception Handling Types and Priority..........................................................

4.1.2

Exception Handling Operation .......................................................................

4.1.3

Exception Vector Table...................................................................................

Reset ...............................................................................................................................

4.2.1

Overview.........................................................................................................

4.2.2

Reset Sequence ...............................................................................................

4.2.3

Interrupts after Reset.......................................................................................

Interrupts.........................................................................................................................

Trap Instruction...............................................................................................................

Stack Status after Exception Handling ...........................................................................

Notes on Stack Usage .....................................................................................................

Section 5

5.1

Interrupt Controller

................................................................................... 81

Overview......................................................................................................................... 81

5.1.1

Features........................................................................................................... 81

5.1.2

Block Diagram................................................................................................ 82

5.2

5.3

5.4

5.5

5.1.3

Pin Configuration............................................................................................ 83

5.1.4

Register Descriptions...................................................................................................... 84

5.2.1

System Control Register (SYSCR)................................................................. 84

5.2.2

Interrupt Priority Registers A and B (IPRA, IPRB) ....................................... 85

5.2.3

IRQ Status Register (ISR) .............................................................................. 92

5.2.4

IRQ Enable Register (IER) ............................................................................. 93

5.2.5

IRQ Sense Control Register (ISCR) ............................................................... 94

Interrupt Sources............................................................................................................. 95

5.3.1

External Interrupts .......................................................................................... 95

5.3.2

Internal Interrupts ........................................................................................... 96

5.3.3

Interrupt Vector Table ..................................................................................... 96

Interrupt Operation ......................................................................................................... 100

5.4.1

Interrupt Handling Process ............................................................................. 100

5.4.2

Interrupt Sequence .......................................................................................... 105

5.4.3

Interrupt Response Time................................................................................. 106

Usage Notes .................................................................................................................... 107

5.5.1

Contention between Interrupt and Interrupt-Disabling Instruction ................ 107

5.5.2

Instructions that Inhibit Interrupts .................................................................. 108

5.5.3

Interrupts during EEPMOV Instruction Execution......................................... 108

5.5.4

Notes on External Interrup to during Use....................................................... 108

Section 6

6.1

Bus Controller

............................................................................................ 111

6.2

6.3

Overview......................................................................................................................... 111

6.1.1

Features........................................................................................................... 111

6.1.2

Block Diagram................................................................................................ 112

6.1.3

Input/Output Pins............................................................................................ 113

6.1.4

Register Descriptions...................................................................................................... 114

6.2.1

Bus Width Control Register (ABWCR) ......................................................... 114

6.2.2

Access State Control Register (ASTCR) ........................................................ 115

6.2.3

Wait Control Register (WCR)......................................................................... 116

6.2.4

Wait State Controller Enable Register (WCER)............................................. 117

6.2.5

Bus Release Control Register (BRCR)........................................................... 118

6.2.6

Chip Select Control Register (CSCR) ............................................................ 119

Operation ........................................................................................................................ 121

6.3.1

Area Division.................................................................................................. 121

6.3.2

Chip Select Signals ......................................................................................... 123

6.3.3

Data Bus.......................................................................................................... 124

6.3.4

Bus Control Signal Timing ............................................................................. 125

6.3.5

Wait Modes ..................................................................................................... 133

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