MCF5271 Reference Manual
Devices Supported:
MCF5270
MCF5271
Document Number: MCF5271RM
Rev. 2
07/2006
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MCF5271RM
Rev. 2
07/2006
Overview
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
Clock Module
Power Management
Chip Configuration Module (CCM)
Reset Controller Module
System Control Module (SCM)
General Purpose I/O Module
Interrupt Controller Modules
DMA Controller Module
Edge Port Module (EPORT)
Chip Select Module
External Interface Module (EIM)
Synchronous DRAM Controller
Fast Ethernet Controller (FEC)
Watchdog Timer Module
Programmable Interrupt Timers (PITs)
DMA Timers
Queued Serial Peripheral Interface (QSPI)
UART Modules
I
2
C interface
Message Digest Hardware Accelerator (MDHA)
Random Number Generator (RNG)
Symmetric Key Hardware Accelerator (SKHA)
IEEE 1149.1 Test Access Port (JTAG)
Debug Support
Register Memory Map Quick Reference
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
IND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
IND
Overview
Signal Descriptions
ColdFire Core
Enhanced Multiply-Accumulate Unit (EMAC)
Cache
Static RAM (SRAM)
Clock Module
Power Management
Chip Configuration Module (CCM)
Reset Controller Module
System Control Module (SCM)
General Purpose I/O Module
Interrupt Controller Modules
DMA Controller Module
Edge Port Module (EPORT)
Chip Select Module
External Interface Module (EIM)
Synchronous DRAM Controller
Fast Ethernet Controller (FEC)
Watchdog Timer Module
Programmable Interrupt Timers (PITs)
DMA Timers
Queued Serial Peripheral Interface (QSPI)
UART Modules
I
2
C interface
Message Digest Hardware Accelerator (MDHA)
Random Number Generator (RNG)
Symmetric Key Hardware Accelerator (SKHA)
IEEE 1149.1 Test Access Port (JTAG)
Debug Support
Register Memory Map Quick Reference
Index
Contents
Paragraph
Number
Title
Page
Number
Chapter 1
Overview
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.5.1
1.3.5.2
1.3.6
1.3.7
1.3.8
1.3.9
1.3.10
1.3.11
1.3.12
1.3.13
1.3.14
1.3.15
1.3.16
1.3.17
1.3.18
1.3.19
1.3.20
1.4
MCF5271 Family Configurations................................................................................... 1-1
Block Diagram ................................................................................................................ 1-2
Features ........................................................................................................................... 1-4
Feature Overview........................................................................................................ 1-4
V2 Core Overview ...................................................................................................... 1-7
Integrated Debug Module ........................................................................................... 1-8
JTAG........................................................................................................................... 1-8
On-chip Memories ...................................................................................................... 1-9
Cache ...................................................................................................................... 1-9
SRAM ..................................................................................................................... 1-9
Fast Ethernet Controller (FEC)................................................................................... 1-9
UARTs ...................................................................................................................... 1-10
I
2
C Bus...................................................................................................................... 1-10
QSPI.......................................................................................................................... 1-10
Cryptography ............................................................................................................ 1-10
DMA Timers (DTIM0-DTIM3) ............................................................................... 1-10
Periodic Interrupt Timers (PIT0-PIT3)..................................................................... 1-10
Software Watchdog Timer........................................................................................ 1-11
Clock Module and Phase Locked Loop (PLL) ......................................................... 1-11
Interrupt Controllers (INTC0, INTC1) ..................................................................... 1-11
DMA Controller........................................................................................................ 1-11
External Interface Module (EIM) ............................................................................. 1-11
SDRAM Controller................................................................................................... 1-12
Reset.......................................................................................................................... 1-12
GPIO ......................................................................................................................... 1-12
Documentation.............................................................................................................. 1-13
Chapter 2
Signal Descriptions
2.1
2.1.1
2.2
2.3
2.3.1
Introduction.....................................................................................................................
Overview.....................................................................................................................
Signal Properties Summary ............................................................................................
Signal Primary Functions................................................................................................
Reset Signals...............................................................................................................
2-1
2-1
2-3
2-7
2-7
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
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