Freescale
Data Sheet: Technical Data
Document Number: MCF52259
Rev. 5, 5/2012
MCF52259 ColdFire
Microcontroller
Supports MCF52252, MCF52254,
MCF52255, MCF52256, MCF52258,
MCF52259
The MCF52259 microcontroller family (MCF52252,
MCF52254, MCF52255, MCF52256, MCF52258, and
MCF52259 devices) is a member of the ColdFire family of
reduced instruction set computing (RISC) microprocessors.
This document provides an overview of the 32-bit MCF52259
microcontroller, focusing on its highly integrated and diverse
feature set.
This 32-bit device is based on the Version 2 ColdFire core
operating at a frequency up to 80 MHz, offering high
performance and low power consumption. On-chip memories
connected tightly to the processor core include up to 512 KB
of flash memory and 64 KB of static random access memory
(SRAM). On-chip modules include:
• V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at
80 MHz running from internal flash memory with
Enhanced Multiply Accumulate (MAC) Unit and hardware
divider
• Cryptography Acceleration Unit (CAU).
• Fast Ethernet controller (FEC)
• Mini-FlexBus external bus interface available on 144 pin
packages
• Universal Serial Bus On-The-Go (USBOTG)
• USB Transceiver
• FlexCAN controller area network (CAN) module
• Three universal asynchronous/synchronous
receiver/transmitters (UARTs)
• Two inter-integrated circuit (I2C) bus interface modules
• Queued serial peripheral interface (QSPI) module
• Eight-channel 12-bit fast analog-to-digital converter
(ADC) with simultaneous sampling
• Four-channel direct memory access (DMA) controller
• Four 32-bit input capture/output compare timers with
DMA support (DTIM)
• Four-channel general-purpose timer (GPT) capable of
input capture/output compare, pulse width modulation
•
•
•
•
•
•
•
•
MCF52259
144 LQFP
20 mm x 20 mm
144 MAPBGA
13 mm x 13 mm
100 LQFP
14 mm x 14 mm
(PWM), pulse-code modulation (PCM), and pulse
accumulation
Eight-channel/Four-channel, 8-bit/16-bit pulse width
modulation timer
Two 16-bit periodic interrupt timers (PITs)
Real-time clock (RTC) module with 32 kHz crystal
Programmable software watchdog timer
Secondary watchdog timer with independent clock
Interrupt controller capable of handling 57 sources
Clock module with 8 MHz on-chip relaxation oscillator
and integrated phase-locked loop (PLL)
Test access/debug port (JTAG, BDM)
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale, Inc., 2011, 2012. All rights reserved.
Table of Contents
1
2
Family Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
2.2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .25
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .26
2.4 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . .28
2.5 EzPort Electrical Specifications . . . . . . . . . . . . . . . . . .29
2.6 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.7 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . .30
2.8 Clock Source Electrical Specifications . . . . . . . . . . . . .31
2.9 USB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
2.10 Mini-FlexBus External Interface Specifications . . . . . .
2.11 Fast Ethernet Timing Specifications . . . . . . . . . . . . . .
2.12 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . .
2.13 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14 I2C Input/Output Timing Specifications . . . . . . . . . . . .
2.15 Analog-to-Digital Converter (ADC) Parameters. . . . . .
2.16 Equivalent Circuit for ADC Inputs . . . . . . . . . . . . . . . .
2.17 DMA Timers Timing Specifications . . . . . . . . . . . . . . .
2.18 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . .
2.19 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . .
2.20 Debug AC Timing Specifications . . . . . . . . . . . . . . . . .
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
33
35
36
37
38
39
40
40
40
43
44
45
3
4
MCF52259 ColdFire Microcontroller, Rev. 5
2
Freescale
Family Configurations
1
Family Configurations
Table 1. MCF52259 Family Configurations
Module
52252
52254
52255
up to
80 MHz
1
52256
52258
52259
up to
80 MHz
1
Version 2 ColdFire Core with eMAC
(Enhanced multiply-accumulate unit) and CAU
(Cryptographic acceleration unit)
System Clock
Performance (Dhrystone 2.1 MIPS)
Flash
Static RAM (SRAM)
Two Interrupt Controllers (INTC)
Fast Analog-to-Digital Converter (ADC)
USB On-The-Go (USB OTG)
Mini-FlexBus external bus interface
Fast Ethernet Controller (FEC)
Random Number Generator and
Cryptographic Acceleration Unit (CAU)
FlexCAN 2.0B Module
Four-channel Direct-Memory Access (DMA)
Software Watchdog Timer (WDT)
Secondary Watchdog Timer
Two-channel Periodic Interrupt Timer (PIT)
Four-Channel General Purpose Timer (GPT)
32-bit DMA Timers
QSPI
UART(s)
I2C
Eight/Four-channel 8/16-bit PWM Timer
General Purpose I/O Module (GPIO)
Chip Configuration and Reset Controller Module
Background Debug Mode (BDM)
JTAG - IEEE 1149.1 Test Access Port
Package
1
up to 66 or 80 MHz
1
up to 66 or 80 MHz
1
up to 63 or 76
256 KB
32 KB
—
—
Varies
2
4
3
2
512 KB
64 KB
—
—
Varies
2
4
3
2
100 LQFP
512 KB
64 KB
—
2
4
3
2
256 KB
32 / 64 KB
—
Varies
2
4
3
2
512 KB
64 KB
—
Varies
2
4
3
2
512 KB
64 KB
2
4
3
2
144 LQFP or 144 MAPBGA
66 MHz = 63 MIPS; 80 MHz = 76 MIPS
MCF52259 ColdFire Microcontroller, Rev. 5
3
Freescale
Family Configurations
1.1
Block Diagram
Figure 1
shows a top-level block diagram of the device. Package options for this family are described later in this document.
EzPD
EzPQ
EzPort
EzPCK
EzPCS
Mini-FlexBus
Interrupt
Controllers
PADI – Pin Muxing
USB
Mini-FlexBus
AN[7:0]
I2Cs
QSPI
UARTs
GPTn
IRQn
FEC
DTINn/DTOUTn
CANRX
CANTX
PWMn
EzPort
JTAG/BDM
To/From PADI
Arbiter
USB
To/From
PADI
FEC
4 ch DMA
To/From PADI
UARTs
0–2
PITs
0–1
I2C
0–1
QSPI
DTIMs
0–3
FlexCAN
Edge
Port
RTC
JTAG_EN
MUX
V2 ColdFire CPU
JTAG
TAP
IFP
OEP
CAU
EMAC
PMM
To/From
PADI
ADC
up to 64 KB
SRAM
(4K16)4
up to 512 KB
Flash
(64K16)4
PORTS
(GPIO)
CCM,
Reset
RSTIN
RSTOUT
V
RH
V
RL
PLL
CLKGEN
Watchdog
Timer
RNGA
GPT
PWM
EXTAL
XTAL CLKOUT
Figure 1. MCF52259 Block Diagram
1.2
1.2.1
•
Features
Feature Overview
Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
MCF52259 ColdFire Microcontroller, Rev. 5
The MCF52259 family includes the following features:
Freescale
4
Family Configurations
—
—
—
—
•
•
•
•
•
Up to 80 MHz processor core frequency
40 MHz or 33 MHz peripheral bus frequency
Sixteen general-purpose, 32-bit data and address registers
Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions
for improved bit processing (ISA_A+)
— Enhanced Multiply-Accumulate (EMAC) unit with four 32-bit accumulators to support 1616
32 or
3232
48 operations
— Cryptographic Acceleration Unit (CAU)
– Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions
– Support for DES, 3DES, AES, MD5, and SHA-1 algorithms
System debug support
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or
2-level trigger
On-chip memories
— Up to 64 KB dual-ported SRAM on CPU internal bus, supporting core, DMA, and USB access with standby
power supply support for the first 16 KB
— Up to 512 KB of interleaved flash memory supporting 2-1-1-1 accesses
Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used (except backup watchdog timer)
— Software controlled disable of external clock output for low-power consumption
FlexCAN 2.0B module
— Based on and includes all existing features of the Freescale TouCAN module
— Full implementation of the CAN protocol specification version 2.0B
– Standard data and remote frames (up to 109 bits long)
– Extended data and remote frames (up to 127 bits long)
– Zero to eight bytes data length
– Programmable bit rate up to 1 Mbit/s
— Flexible message buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length each, configurable as
Rx or Tx, all supporting standard and extended messages
— Unused MB space can be used as general purpose RAM space
— Listen-only mode capability
— Content-related addressing
— No read/write semaphores
— Three programmable mask registers: global for MBs 0–13, special for MB14, and special for MB15
— Programmable transmit-first scheme: lowest ID or lowest buffer number
— Time stamp based on 16-bit free-running timer
— Global network time, synchronized by a specific message
— Maskable interrupts
Universal Serial Bus On-The-Go (USB OTG) dual-mode host and device controller
— Full-speed / low-speed host controller
— USB 1.1 and 2.0 compliant full-speed / low speed device controller
— 16 bidirectional end points
MCF52259 ColdFire Microcontroller, Rev. 5
5
Freescale
微控制器 MCU
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