Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF52211
Rev. 2, 3/2011
MCF52211
MCF52211 ColdFire
Microcontroller
Supports
MCF52210 / 52211 /
52212 / 52213
The MCF52211 microcontroller family is a member of the
ColdFire
®
family of reduced instruction set computing
(RISC) microprocessors.
This document provides an overview of the 32-bit MCF52211
microcontroller, focusing on its highly integrated and diverse
feature set.
This 32-bit device is based on the Version 2 ColdFire core
operating at a frequency up to 80 MHz, offering high
performance and low power consumption. On-chip memories
connected tightly to the processor core include up to
128 Kbytes of flash memory and 16 Kbytes of static random
access memory (SRAM). On-chip modules include:
• V2 ColdFire core delivering 76 MIPS (Dhrystone 2.1) at
80 MHz running from internal flash memory with Multiply
Accumulate (MAC) Unit and hardware divider
• Universal Serial Bus On-The-Go (USBOTG)
• USB Transceiver
• Three universal asynchronous/synchronous
receiver/transmitters (UARTs)
• Two inter-integrated circuit (I2C™) bus interface modules
• Queued serial peripheral interface (QSPI) module
• Eight-channel 12-bit fast analog-to-digital converter
(ADC)
• Four-channel direct memory access (DMA) controller
• Four 32-bit input capture/output compare timers with
DMA support (DTIM)
• Four-channel general-purpose timer (GPT) capable of
input capture/output compare, pulse width modulation
(PWM), and pulse accumulation
• Eight-channel/Four-channel, 8-bit/16-bit pulse width
modulation timer
• Two 16-bit periodic interrupt timers (PITs)
• Real-time clock (RTC) module
• Programmable software watchdog timer
• Interrupt controller capable of handling 57 sources
LQFP–64
10 mm x 10 mm
QFN–64
9 mm x 9 mm
MAPBGA–81
10 mm x 10 mm
LQFP–100
14 mm x 14 mm
• Clock module with 8 MHz on-chip relaxation oscillator
and integrated phase-locked loop (PLL)
• Test access/debug port (JTAG, BDM)
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2011. All rights reserved.
Table of Contents
1
Family Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Reset Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.4 PLL and Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.6 External Interrupt Signals . . . . . . . . . . . . . . . . . . . . . . .21
1.7 Queued Serial Peripheral Interface (QSPI). . . . . . . . . .21
1.8 USB On-the-Go. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.9 I
2
C I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.10 UART Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.11 DMA Timer Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.12 ADC Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.13 General Purpose Timer Signals . . . . . . . . . . . . . . . . . .23
1.14 Pulse Width Modulator Signals . . . . . . . . . . . . . . . . . . .23
1.15 Debug Support Signals . . . . . . . . . . . . . . . . . . . . . . . . .23
1.16 EzPort Signal Descriptions . . . . . . . . . . . . . . . . . . . . . .24
1.17 Power and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . .25
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28
2.4 Flash Memory Characteristics . . . . . . . . . . . . . . . . . . .
2.5 EzPort Electrical Specifications . . . . . . . . . . . . . . . . . .
2.6 ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 DC Electrical Specifications. . . . . . . . . . . . . . . . . . . . .
2.8 Clock Source Electrical Specifications . . . . . . . . . . . .
2.9 USB Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 General Purpose I/O Timing . . . . . . . . . . . . . . . . . . . .
2.11 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.12 I
2
C Input/Output Timing Specifications . . . . . . . . . . . .
2.13 Analog-to-Digital Converter (ADC) Parameters. . . . . .
2.14 Equivalent Circuit for ADC Inputs . . . . . . . . . . . . . . . .
2.15 DMA Timers Timing Specifications . . . . . . . . . . . . . . .
2.16 QSPI Electrical Specifications . . . . . . . . . . . . . . . . . . .
2.17 JTAG and Boundary Scan Timing . . . . . . . . . . . . . . . .
2.18 Debug AC Timing Specifications . . . . . . . . . . . . . . . . .
Mechanical Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . .
3.1 64-pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 64 QFN Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 81 MAPBGA Package . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 100-pin LQFP Package . . . . . . . . . . . . . . . . . . . . . . . .
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
30
31
31
32
33
33
34
35
36
37
38
38
38
41
42
43
46
50
52
54
3
2
4
MCF52211 ColdFire Microcontroller, Rev. 2
2
Freescale Semiconductor
Family Configurations
1
Family Configurations
Table 1. MCF52211 Family Configurations
Module
52210
52211
52212
52213
Version 2 ColdFire Core with MAC
(Multiply-Accumulate Unit)
System Clock
Performance (Dhrystone 2.1 MIPS)
Flash / Static RAM (SRAM)
Interrupt Controller (INTC)
Fast Analog-to-Digital Converter (ADC)
USB On-The-Go (USB OTG)
Four-channel Direct-Memory Access (DMA)
Software Watchdog Timer (WDT)
Secondary Watchdog Timer
Two-channel Periodic Interrupt Timer (PIT)
Four-Channel General Purpose Timer (GPT)
32-bit DMA Timers
QSPI
UART(s)
66, 80 MHz
up to 76
64/16 Kbytes
50 MHz
up to 46
64/8 Kbytes
128/16 Kbytes
128/8 Kbytes
2
2
2
2
4
4
4
4
2
2 (64 LQFP/QFN and
81 MAPBGA)
3 (100 LQFP)
2
2
2
I
2
C
Eight/Four-channel 8/16-bit PWM Timer
General Purpose I/O Module (GPIO)
Chip Configuration and Reset Controller Module
Background Debug Mode (BDM)
JTAG - IEEE 1149.1 Test Access Port
1
Package
2
2
2
64 LQFP/QFN
81 MAPBGA
64 LQFP/QFN
81 MAPBGA
100 LQFP
64 LQFP
64 LQFP
1
The full debug/trace interface is available only on the 100-pin packages. A reduced debug interface is bonded on smaller
packages.
MCF52211 ColdFire Microcontroller, Rev. 2
3
Freescale Semiconductor
Family Configurations
1.1
Block Diagram
Figure 1
shows a top-level block diagram of the device. Package options for this family are described later in this document.
Slave Mode Access
(CIM_IBO/EzPort)
AN
QSPI
SDAn
SCLn
UTXDn
PADI – Pin Muxing
URXDn
URTSn
UCTSn
PWMn
DTINn/DTOUTn
GPT
RCON_B
ALLPST
PST
DDATA
M1
TMS
TDI
TDO
TRST
TCLK
Arbiter
M2 M0
M3
Interrupt
Controller
BDM
PORT
UART
0
UART
1
UART
2
I
2
C
QSPI
Watch
Dog
JTAG
TAP
JTAG_EN
USB
On-The-Go
USB TCVR
USBD+
USBD-
IPS Bus Gasket
AN[7:0]
CIM_IBO
ADC
Backup
Watchdog
TMR
0
TMR
1
TMR
2
TMR
3
RTC
I
2
C
4 CH
DMA
V2 ColdFire CPU
PMM
16 Kbytes
SRAM
(2K32)2
CFM
128 Kbytes
Flash
(16K16)4
V
PP
CLKMOD
PORTS
CIM_IBO
RSTI
RSTO
V
STBY
TIM
Edge
Port
EXTAL
IRQ[7:1]
PLL OCO
CLKGEN
XTAL
CLKOUT
PIT0
PIT1
PWM
GPT[3:0]
Figure 1. Block Diagram
MCF52211 ColdFire Microcontroller, Rev. 2
Freescale Semiconductor
4
Family Configurations
1.2
1.2.1
•
Features
Feature Overview
Version 2 ColdFire variable-length RISC processor core
— Static operation
— 32-bit address and data paths on-chip
— Up to 80 MHz processor core frequency
— 40 MHz and 33 MHz off-platform bus frequency
— Sixteen general-purpose, 32-bit data and address registers
— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions
for improved bit processing (ISA_A+)
— Multiply-Accumulate (MAC) unit with 32-bit accumulator to support 1616
32 or 3232
32 operations
System debug support
— Real-time trace for determining dynamic execution path
— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)
— Real-time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) configurable into a 1- or
2-level trigger
On-chip memories
— Up to 16-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power
supply support
— Up to 128 Kbytes of interleaved flash memory supporting 2-1-1-1 accesses
Power management
— Fully static operation with processor sleep and whole chip stop modes
— Rapid response to interrupts from the low-power sleep mode (wake-up feature)
— Clock enable/disable for each peripheral when not used (except backup watchdog timer)
— Software controlled disable of external clock output for low-power consumption
Universal Serial Bus On-The-Go (USB OTG) dual-mode host and device controller
— Full-speed / low-speed host controller
— USB 1.1 and 2.0 compliant full-speed / low speed device controller
— 16 bidirectional end points
— DMA or FIFO data stream interfaces
— Low power consumption
— OTG protocol logic
Three universal asynchronous/synchronous receiver transmitters (UARTs)
— 16-bit divider for clock generation
— Interrupt control logic with maskable interrupts
— DMA support
— Data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity
— Up to two stop bits in 1/16 increments
— Error-detection capabilities
— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs
— Transmit and receive FIFO buffers
Two I
2
C modules
The MCF52211 family includes the following features:
•
•
•
•
•
•
MCF52211 ColdFire Microcontroller, Rev. 2
5
Freescale Semiconductor
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