FemtoClock®, Crystal-to-LVCMOS/LVTTL
Frequency Synthesizer
840002-01
DATA SHEET
General Description
The 840002-01 is a two output LVCMOS/LVTTL Synthesizer
optimized to generate Ethernet reference clock frequencies. Using a
25MHz 18pF parallel resonant crystal, the following frequencies can
be generated based on the two frequency select pins (F_SEL[1:0]):
156.25MHz, 125MHz, and 62.5MHz. The 840002-01 uses IDT’s 3
RD
generation low phase noise VCO technology and can achieve 1ps or
lower typical random rms phase jitter, easily meeting Ethernet jitter
requirements. The 840002-01 is packaged in a small 16-pin TSSOP
package.
Features
•
•
•
•
•
•
Two LVCMOS/LVTTL outputs@ 3.3V,
17 typical output impedance
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended TEST_CLK
Output frequency range: 56MHz to 175MHz
VCO range: 560MHz to 700MHz
Output skew: 12ps (maximum)
RMS phase jitter at 156.25MHz, (1.875MHz to 20MHz):
0.47ps (typical)
Phase Noise:
Offset
Noise Power
100Hz.................-97.4 dBc/Hz
1kHz ...................-120.2 dBc/Hz
10kHz .................-127.6 dBc/Hz
100kHz ...............-126.1 dBc/Hz
•
•
•
Frequency Select Function Table
Inputs
F_SEL1
0
0
1
1
F_SEL0
0
1
0
1
M Divider Value
25
25
25
25
N Divider Value
4
5
10
5
Full 3.3V or mixed 3.3V core/2.5V output supply modes
-30°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Output Frequency (25MHz Ref.)
156.25
125
62.5
125
Block Diagram
OE
F_SEL1:0
nPLL_SEL
nXTAL_SEL
XTAL_IN
Pullup
Pullup:Pullup
Pulldown
Pulldown
Pin Assignment
2
F_SEL0
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
V
DDA
V
DD
F_SEL1:0
Q0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
F_SEL1
GND
GND
Q0
Q1
V
DDO
XTAL_IN
XTAL_OUT
OSC
XTAL_OUT
TEST_CLK
Pulldown
0
840002-01
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
G Package
Top View
1
Phase
Detector
00
01
10
11
1
VCO
0
N
÷4
÷5
÷10
÷5
Q1
M = ÷25 (fixed)
MR
Pulldown
840002-01 Rev E 11/12/14
1
©2014 Integrated Device Technology, Inc.
840002-01 DATA SHEET
Table 1. Pin Descriptions
Number
1
2
3
4
Name
F_SEL0
nXTAL_SEL
TEST_CLK
OE
Input
Input
Input
Input
Type
Pullup
Pulldown
Pulldown
Pullup
Description
Frequency select pin. LVCMOS/LVTTL interface levels.
Selects between crystal or TEST_CLK inputs as the PLL reference
source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
Single-ended test clock input. LVCMOS/LVTTL interface levels.
Output enable. When logic HIGH, the outputs are active.
When LOW, the outputs are in high-impedance state.
LVCMOS/LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the active outputs to go low. When Logic LOW,
the internal dividers and the outputs are enabled. LVCMOS/LVTTL
interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output. When
HIGH, the PLL is bypassed and the output frequency = reference clock
frequency/N output divider. LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the
output.
Output supply pin.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
5
MR
Input
Pulldown
6
7
8
9,
10
11
12, 13
14, 15
16
nPLL_SEL
V
DDA
V
DD
XTAL_OUT
XTAL_IN
V
DDO
Q1, Q0
GND
F_SEL1
Input
Power
Power
Input
Power
Output
Power
Input
Pulldown
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DDO
= 3.3V ± 5%
V
DDO
= 2.5V ± 5%
14
16
Test Conditions
Minimum
Typical
4
8
51
51
17
21
21
25
Maximum
Units
pF
pF
k
k
Rev E 11/12/14
2
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
840002-01 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
-0.5V to V
DDO
+ 0.5V
89C/W (0 lfpm)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5% or 2.5V±5%, T
A
= -30°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
2.375
Power Supply Current
Analog Supply Current
Output Supply Current
2.5
2.625
100
12
5
V
mA
mA
mA
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
Units
V
V
V
Table 3B. LVCMOS/LVTTL DC Characteristics,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5% or 2.5V±5%, T
A
= -30°C to 85°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
OE, F_SEL0, F_SEL1
Input
High Current
MR, TEST_CLK,
nXTAL_SEL, nPLL_SEL
OE, F_SEL0, F_SEL1
I
IL
Input
Low Current
MR, TEST_CLK,
nXTAL_SEL, nPLL_SEL
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= V
IN
=3.465V or 2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
V
DDO
= 3.3V±5%
V
DDO
= 2.5V±5%
Output Low Voltage; NOTE 1
V
DDO
= 3.3V±5% or 2.5V±5%
-150
-5
2.6
1.8
0.5
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
150
Units
V
V
µA
µA
µA
µA
V
V
V
V
OH
V
OL
Output High Voltage; NOTE 1
NOTE 1: Outputs terminated with 50
to V
DDO
/2. See Parameter Measurement Information section,
Output Load Test Circuit diagrams.
Rev E 11/12/14
3
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
840002-01 DATA SHEET
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance (C
O
)
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
Test Conditions
Minimum
Typical
Fundamental
25
50
7
1
MHz
Maximum
Units
pF
mW
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -30°C to 85°C
Symbol
f
OUT
tsk(o)
tjit(Ø)
t
R
/ t
F
odc
Parameter
Output Frequency
Output Skew; NOTE 1, 2
156.25MHz, (1.875MHz - 20MHz)
RMS Phase Jitter, Random;
NOTE 3
Output Rise/Fall Time
Output Duty Cycle
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
20% to 80%
200
46
0.47
0.57
0.51
700
54
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01 or 11
F_SEL[1:0] = 10
Minimum
140
112
56
Typical
Maximum
175
140
70
12
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Refer to Phase Noise Plot.
Table 5B. AC Characteristics,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 2.5V±5%, T
A
= -30°C to 85°C
Symbol
f
OUT
tsk(o)
tjit(Ø)
t
R
/ t
F
odc
Parameter
Output Frequency
Output Skew; NOTE 1, 2
156.25MHz, (1.875MHz - 20MHz)
RMS Phase Jitter, Random;
NOTE 3
Output Rise/Fall Time
Output Duty Cycle
125MHz, (1.875MHz - 20MHz)
62.5MHz, (1.875MHz - 20MHz)
20% to 80%
f
OUT
= 125MHz
200
46
47
0.47
0.55
0.49
700
54
53
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01 or 11
F_SEL[1:0] = 10
Minimum
140
112
56
Typical
Maximum
175
140
70
12
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
%
For NOTES, see Table 5A above.
Rev E 11/12/14
4
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
840002-01 DATA SHEET
Typical Phase Noise at 62.5MHz (3.3V)
➝
1Gb Ethernet Filter
Noise Power
dBc
Hz
62.5MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.51ps (typical)
Offset Frequency (Hz)
Typical Phase Noise at 156.25MHz (3.3V)
➝
Noise Power
dBc
Hz
Offset Frequency (Hz)
Rev E 11/12/14
5
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.47ps (typical)
Raw Phase Noise Data
➝
Phase Noise Result by adding a
10Gb Ethernet filter to raw data
➝
10Gb Ethernet Filter
➝
Raw Phase Noise Data
Phase Noise Result by adding a
1Gb Ethernet filter to raw data
➝
FEMTOCLOCK®, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY
SYNTHESIZER
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
