Freescale Semiconductor, Inc.
MC56F8357/D
Rev. 7.0, 06/2004
56F8357
Preliminary Technical Data
56F8357 16-bit Digital Signal Processor
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Temperature Sensor
• Two Quadrature Decoders
• Optional on-chip regulator
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 76 GPIO lines
• 160-pin LQFP Package
OCR_DIS
V
DD
V
SS
7
6
Digital Reg
Freescale Semiconductor, Inc...
• Access up to 4MB of off-chip program and 32MB
of data memory
• Chip Select Logic for glueless interface to ROM
and SRAM
• 256KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 16KB of Data RAM
• 16KB Boot Flash
• Two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
RSTO
EMI_MODE
EXTBOOT
5
JTAG/
EOnCE
Port
V
PP
2
V
CAP
4
V
DDA
2
V
SSA
RESET
6
3
4
6
3
4
4
4
5
4
4
* Configuration
shown for on-chip
2.5V regulator
PWM Outputs
PWMA
Analog Reg
Current Sense Inputs or GPIOC
Fault Inputs
PWM Outputs
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
PWMB
Current Sense Inputs or GPIOD
Fault Inputs
AD0
AD1
VREF
AD0
AD1
TEMP_SENSE
Quadrature
Decoder 0 or
Quad
Timer or /
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or GPIOC
Quad
Timer C or
GPIOE
Quad
Timer D or
GPIOE
FlexCAN
SPI0 or
GPIOE
4
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
ADCA
PAB
PDB
CDBR
CDBW
Memory
ADCB
Program Memory
128K x 16 Flash
2K x 16 RAM
Boot ROM
8K x 16 Flash
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
External
Address Bus
Switch
6
2
8
4
1
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0-3 (A16-19)
GPIOB4 (A20,
prescaler_clock)
GPIOB5-7 (A21-23,
clk0-3**)
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
GPIOD0-5 or CS2-7
PS (CS0) or GPIOD8
DS (CS1) or GPIOD9
**See Table 2-2
for explanation
External Bus
Interface Unit
System Bus
Control
3
7
8
4
Data Memory
4K x 16 Flash
8K x 16 RAM
External Data
Bus Switch
4
IPBus Bridge (IPBB)
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
Bus Control
6
2
Decoding
Peripherals
Clock
resets
PLL
4
2
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Watchdog
Interrupt
Controller
P
System
O
Integration
R
Module
O
Clock
S
Generator
C
XTAL
EXTAL
IRQA
IRQB
CLKO
CLKMODE
56F8357 Block Diagram
© Motorola, Inc., 2004. All rights reserved.
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Document Revision History
Version History
Rev 1.0
Rev 2.0
Description of Change
Initial Public Release
Added Package Pins to GPIO Table in
Part 8, General Purpose Input/Output (GPIO)
Added “Typical Min” values to
Table 10-17
Editing grammar, spelling, consistency of language throughout family
Updated values in Regulator Parameters
Table 10-9,
External Clock Operation Timing Requirements
Table 10-13,
SPI Timing
Table 10-18,
ADC Parameters
Table 10-24,
and
IO Loading Coefficients at 10MHz
Table 10-25.
Rev 3.0
Rev 4.0
Corrected
Table 4-6
Data Memory Map - changed address X:$FF0000 to X:$FFFF00
Added
Section 4.8,
added the word “access” to FM Error Interrupt in
Table 4-5,
documenting only Typ. numbers for LVI in
Table 10-6,
updated EMI numbers and writeup in
Section 10.9.
Updated numbers in
Table 10-7
and
Table 10-8
with more recent data,
Corrected typo in
Table 10-3
in Pd characteristics.
Replace any reference to Flash Interface Unit with Flash Module; removed references to
JTAG pin DE; corrected pin number for D14 in
Table 2-2;
added note to Vcap pin in
Table 2-2;
corrected thermal numbers for 160 LQFP in
Table 10-3;
removed unneccessary
notes in
Table 10-12;
corrected temperature range in
Table 10-14;
added ADC calibration
information to
Table 10-24
and new graphs in
Figure 10-22
Adding/clarifing notes to
Table 4-4
to help clarify independent program flash blocks and
other Program Flash modes, clarification in
Table 10-23,
corrected Digital Input Current
Low (pull-up enabled) numbers in
Table 10-5.
Removed text and Table 10-2; replaced with
note to
Table 10-1.
Freescale Semiconductor, Inc...
Rev 5.0
Rev 6.0
Rev 7.0
2
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56F8357 Technical Data
Preliminary
Freescale Semiconductor, Inc.
56F8357 Data Sheet Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . 4
1.1. 56F8357 Features . . . . . . . . . . . . . . . . . . 4
1.2. 56F8357 Description . . . . . . . . . . . . . . . . 5
1.3. Award-Winning Development
Environment . . . . . . . . . . . . . . . 6
1.4. Architecture Block Diagram . . . . . . . . . . . 7
1.5. Product Documentation . . . . . . . . . . . . . 10
1.6. Data Sheet Conventions . . . . . . . . . . . . 11
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . 118
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . 118
8.2. Configuration . . . . . . . . . . . . . . . . . . . . 118
8.3. Memory Maps . . . . . . . . . . . . . . . . . . . 122
Part 9: Joint Test Action Group (JTAG) 122
9.1. 56F8357 Information . . . . . . . . . . . . . . 122
Part 2: Signal/Connection Descriptions 12
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 12
2.2. 56F8357 Signal Pins . . . . . . . . . . . . . . . 14
Part 10: Specifications . . . . . . . . . . . . . 122
10.1. General Characteristics . . . . . . . . . . . 122
10.2. DC Electrical Characteristics . . . . . . . 126
10.3. Temperature Sense . . . . . . . . . . . . . . 129
10.4. AC Electrical Characteristics . . . . . . . 129
10.5. Flash Memory Characteristics . . . . . . 130
10.6. External Clock Operation Timing . . . . 131
10.7. Phase Locked Loop Timing . . . . . . . . 131
10.8. Crystal Oscillator Timing . . . . . . . . . . 132
10.9. External Memory Interface Timing . . . 132
10.10. Reset, Stop, Wait, Mode Select,
and Interrupt Timing . . . . . . . 135
10.11. Serial Peripheral Interface (SPI)
Timing . . . . . . . . . . . . . . . . . . 137
10.12. Quad Timer Timing . . . . . . . . . . . . . 141
10.13. Quadrature Decoder Timing . . . . . . . 141
10.14. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . 142
10.15. Controller Area Network (CAN)
Timing . . . . . . . . . . . . . . . . . . 143
10.16. JTAG Timing . . . . . . . . . . . . . . . . . . 143
10.17. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . 145
10.18. Equivalent Circuit for ADC Inputs . . . 147
10.19. Power Consumption . . . . . . . . . . . . . 147
Freescale Semiconductor, Inc...
Part 3: On-Chip Clock Synthesis (OCCS) 32
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 32
3.2. External Clock Operation . . . . . . . . . . . 33
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . 34
Part 4: Memory Operating Modes (MEM) 35
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
Introduction . . . . . . . . . . . . . . . . . . . . . .
Program Map . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Table . . . . . . . . . . . . . .
Data Map . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Map . . . . . . . . . . . . . . . .
EOnCE Memory Map . . . . . . . . . . . . . .
Peripheral Memory Mapped Registers .
Factory Programmed Memory . . . . . . . .
35
36
37
40
40
42
42
68
Part 5: Interrupt Controller (ITCN) . . . . . 69
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
Introduction . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . .
69
69
69
71
71
72
96
Part 11: Packaging . . . . . . . . . . . . . . . . 149
11.1. Package and Pin-Out Information
56F8357 . . . . . . . . . . . . . . . . 149
Part 6: System Integration Module (SIM) 97
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
Overview . . . . . . . . . . . . . . . . . . . . . . . . 97
Features . . . . . . . . . . . . . . . . . . . . . . . . 97
Operating Modes . . . . . . . . . . . . . . . . . . 98
Operation Mode Register . . . . . . . . . . . 98
Register Descriptions . . . . . . . . . . . . . . 99
Clock Generation Overview . . . . . . . . 111
Power Down Modes Overview . . . . . . 112
Stop and Wait Mode Disable Function 112
Resets . . . . . . . . . . . . . . . . . . . . . . . . . 113
Part 12: Design Considerations . . . . . . 153
12.1. Thermal Design Considerations . . . . . 153
12.2. Electrical Design Considerations . . . . 154
12.3. Power Distribution and I/O Ring
Implementation 155
Part 13: Ordering Information . . . . . . . 156
Part 7: Security Features . . . . . . . . . . . 114
7.1. Operation with Security Enabled . . . . . 114
7.2. Flash Access Blocking Mechanisms . . 114
Please see http://www.motorola.com/semiconductors for the most current Data Sheet revision.
56F8357 Technical Data
Preliminary
For More Information On This Product,
Go to: www.freescale.com
3
Freescale Semiconductor, Inc.
Part 1 Overview
1.1 56F8357 Features
1.1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Digital Signal Processing Core
Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture
As many as 60 Million Instructions Per Second (MIPS) at 60 MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
Freescale Semiconductor, Inc...
1.1.2
•
•
•
Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security protection feature
On-chip memory, including a low-cost, high-volume flash solution
— 256KB of Program Flash
— 4KB of Program RAM
— 8KB of Data Flash
— 16KB of Data RAM
— 16KB of Boot Flash
•
Off-chip memory expansion capabilities provide a simple method for interfacing additional external
memory and/or peripheral devices
— Access up to 4MB of external program memory or 32MB of external data memory
—
— external accesses supported at up to 60MHz (zero wait states)
•
EEPROM emulation capability
1.1.3
•
•
Peripheral Circuits for 56F8357
Two Pulse Width Modulator modules, each with six PWM outputs, three Current Sense inputs, and
four Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and
edge-aligned modes
Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions
with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer
C, channels 2 and 3
4
For More Information On This Product,
Go to: www.freescale.com
56F8357 Technical Data
Preliminary
Freescale Semiconductor, Inc.
56F8357 Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Freescale Semiconductor, Inc...
Temperature Sensor can be connected, on the board, to any of the ADC inputs to monitor the
on-chip temperature
Two four-input Quadrature Decoders or two additional Quad Timers
Four dedicated general-purpose Quad Timers totaling dedicated six pins: Timer C with two pins and
Timer D with four pins
FlexCAN (CAN Version 2.0 B-compliant ) module with 2-pin port for transmit and receive
Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines)
Two Serial Peripheral Interfaces (SPIs). both with configurable 4-pin port (or eight additional GPIO
lines); SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B
Computer Operating Properly (COP) / Watchdog timer
Two dedicated external interrupt pins
Up to 76 General Purpose I/O (GPIO) pins
External reset input pin for hardware reset
External reset output pin for system reset
Integrated Low-Voltage Interrupt Module
JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent
debugging
Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the core clock
1.1.4
•
•
•
•
•
•
Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be
disabled
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
ADC smart power management
Each peripheral can be individually disabled to save power
1.2 56F8357 Description
The 56F8357 is a member of the 56800E core-based family of hybrid controllers. It combines, on
a single chip, the processing power of a DSP and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56F8357 is well-suited for many
applications. The 56F8357 includes many peripherals that are especially useful for motion control,
smart appliances, steppers, encoders, tachometers, limit switches, power supply and control,
automotive control, engine management, noise suppression, remote utility metering, industrial
control for power, lighting, and automation applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units
operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style
programming model and optimized instruction set allow straightforward generation of efficient,
compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to
enable rapid development of optimized control applications.
The 56F8357 supports program execution from internal or external memories. Two data operands
can be accessed from the on-chip data RAM per instruction cycle. The 56F8357 also provides two
external dedicated interrupt lines and up to 76 General Purpose Input/Output (GPIO) lines,
depending on peripheral configuration.
56F8357 Technical Data
Preliminary
For More Information On This Product,
Go to: www.freescale.com
5
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