Preliminary
GS8182D18D-333/300/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
Features
• Simultaneous Read and Write SigmaQuad™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• Burst of 4 Read and Write
• 1.8 V +150/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices
- 333
tKHKH
tKHQV
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.50 ns
18Mb
Σ
2x2B4
SigmaQuad-II SRAM
167 MHz – 333 MHz
1.8 V V
DD
1.8 V and 1.5 V I/O
Bottom View
165-Bump, 13 mm x 15 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
JEDEC Std. MO-216, Variation CAB-1
Because Separate I/O
Σ
2x2B4 RAMs always transfer data in four
packets, A0 and A1 are internally set to 0 for the first read or write
transfer, and automatically incremented by 1 for the next transfers.
Because the LSBs are tied off internally, the address field of a
Σ
2x2B4 RAM is always two address pins less than the advertised
index depth (e.g., the 1M x 18 has a 256K addressable index).
SigmaRAM™ Family Overview
GS8182D18 are built in compliance with the SigmaQuad-II SRAM
pinout standard for Separate I/O synchronous SRAMs. They are
18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide,
very low voltage HSTL I/O SRAMs designed to operate at the speeds
needed to implement economical high performance networking
systems.
two input register clock inputs, K and K. K and K are independent
single-ended clock inputs, not differential inputs to a single differential
clock input buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and C
clock inputs. C and C are also independent single-ended clock inputs,
not differential inputs. If the C clocks are tied high, the K clocks are
routed internally to fire the output registers instead.
Clocking and Addressing Schemes
A
Σ
2x2B4 SigmaQuad-II SRAM is a synchronous device. It employs
Rev: 1.01a 8/2003
1/27
© 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8182D18D-333/300/250/200/167
1M x 18 SigmaQuad-II SRAM — Top View
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
D
off
NC
NC
NC
NC
NC
NC
TDO
2
MCL/SA
(144Mb)
Q9
NC
D11
NC
Q12
D13
V
REF
NC
NC
Q15
NC
D17
NC
TCK
3
NC/SA
(36Mb)
D9
D10
Q10
Q11
D12
Q13
V
DDQ
D14
Q14
D15
D16
Q16
Q17
SA
4
W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
5
BW1
NC
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
6
K
K
NC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
7
NC
BW0
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
8
R
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
10
MCL/SA
(72Mb)
NC
Q7
NC
D6
NC
NC
V
REF
Q4
D3
NC
Q1
NC
D0
TMS
11
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Expansion addresses: A3 for 36Mb, A10 for 72Mb, A2 for 144Mb
2. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
3. MCL = Must Connect Low
4. It is recommended that H1 be tied low for compatibility with future devices.
Rev: 1.01a 8/2003
2/27
© 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8182D18D-333/300/250/200/167
Pin Description Table
Symbol
SA
NC
R
W
BW0–BW1
K
K
C
C
TMS
TDI
TCK
TDO
V
REF
ZQ
MCL
D0–D17
Q0–Q17
D
off
CQ
CQ
V
DD
V
DDQ
V
SS
Description
Synchronous Address Inputs
No Connect
Synchronous Read
Synchronous Write
Synchronous Byte Writes
Input Clock
Input Clock
Output Clock
Output Clock
Test Mode Select
Test Data Input
Test Clock Input
Test Data Output
HSTL Input Reference Voltage
Output Impedance Matching Input
Must Connect Low
Synchronous Data Inputs
Synchronous Data Outputs
Disable DLL when low
Output Echo Clock
Output Echo Clock
Power Supply
Isolated Output Buffer Supply
Power Supply: Ground
Type
Input
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
—
Input
Output
Input
Output
Output
Supply
Supply
Supply
Comments
—
—
Active Low
Active Low
Active Low
Active High
Active Low
Active High
Active Low
—
—
—
—
—
—
—
—
—
Active Low
—
—
2.5 V Nominal
1.5 V Nominal
—
Note: NC = Not Connected to die or any other pin
Rev: 1.01a 8/2003
3/27
© 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8182D18D-333/300/250/200/167
Background
Separate I/O SRAMs, from a system architecture point of view, are attractive in applications where alternating reads and writes are needed.
Therefore, the SigmaQuad-II SRAM interface and truth table are optimized for alternating reads and writes. Separate I/O SRAMs are unpopular
in applications where multiple reads or multiple writes are needed because burst read or write transfers from Separate I/O SRAMs can cut the
RAM’s bandwidth in half.
A SigmaQuad-II SRAM can begin an alternating sequence of reads and writes with either a read or a write. In order for any separate I/O SRAM
that shares a common address between its two ports to keep both ports running all the time, the RAM must implement some sort of burst transfer
protocol. The burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do next. The rate at which
a RAM can accept a new random address is the most fundamental performance metric for the RAM. Each of the three SigmaQuad-II SRAMs
support similar address rates because random address rate is determined by the internal performance of the RAM and they are all based on the
same internal circuits. Differences between the truth tables of the different SigmaQuad-II SRAMs, or any other Separate I/O SRAMs, follow from
differences in how the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and
disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application
at hand.
Alternating Read-Write Operations
SigmaQuad-II SRAMs follow a few simple rules of operation.
- Read or Write commands issued on one port are never allowed to interrupt an operation in progress on the other port.
- Read or Write data transfers in progress may not be interrupted and re-started.
- R and W high always deselects the RAM.
- All address, data, and control inputs are sampled on clock edges.
In order to enforce these rules, each RAM combines present state information with command inputs. See the Truth Table for details.
Rev: 1.01a 8/2003
4/27
© 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
Preliminary
GS8182D18D-333/300/250/200/167
The status of the Address Input, W, and R pins are sampled at each rising edge of K. W and R high causes chip disable. A low on the Read
Enable-bar pin, R, begins a read cycle. R is always ignored if the previous command loaded was a read command. The four resulting data output
transfers begin after the next rising edge of the K clock. Data is clocked out by the next rising edge of the C, the rising edge of C after that, the
next rising edge of C, and finally by the next rising edge of C.
Σ
2x2B4 SigmaQuad-II SRAM DDR Read
Σ
2x2B4 Double Data Rate SigmaQuad-II SRAM Read First
Read A
KHKH
K
KHKHbar
Kbar
KHAX
AVKH
Address
A
B
C
D
E
NOP
KHKL
KLKH
Read B
Write C
Read D
Write E
NOP
KHBX
BVKH
Rbar
KHBX
BVKH
Wbar
KHDX
DVKH
DVKH
KHDX
D
KHKL
KHKH
C
KHKHbar
Cbar
CHQV
CHQX1
CHQV
CHQX
Q
CQHQV
CQHQX
CQ
CQHQV
CQHQX
CQbar
A
A+1
A+2
C
C+1
C+2
C+3
KHDX
DVKH
DVKH
KHDX
E
E+1
E+2
E+3
KLKH
CHQV
CHQX
CHQV
CHQX
A+3
B
CHQV
CHQX
CHQV
CHQX
B+1
B+2
CHQV
CHQX
CHQV
CHQX
B+3
D
CHQV
CHQX
CHQV
CHQX
D+1
D+2
CHQX
CHQZ
Rev: 1.01a 8/2003
5/27
© 2003, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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