FemtoClock
®
Crystal-to-LVDS
Frequency Synthesizer
NRND – Not Recommend for New Designs
ICS844004I-01
NRND
DATA SHEET
General Description
The ICS844004I-01 is a 4 output LVDS Synthesizer optimized to
generate Ethernet reference clock frequencies. Using a 25MHz
18pF parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
156.25MHz, 125MHz and 62.5MHz. The ICS844004I-01 uses IDT’s
3
rd
generation low phase noise VCO technology and can achieve
<1ps typical rms phase jitter, easily meeting Ethernet jitter
requirements. The ICS844004I-01 is packaged in a small 24-pin
TSSOP package.
Features
•
•
•
•
•
•
•
•
•
Four LVDS output pairs
Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
Supports the following output frequencies: 156.25MHz, 125MHz,
62.5MHz
VCO range: 560MHz - 680MHz
RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.41ps (typical)
Full 3.3V or 2.5V supply modes
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Not Recommended For New Designs
Frequency Select Function Table
Inputs
F_SEL1
0
0
1
1
F_SEL0
0
1
0
1
M Div. Value
25
25
25
25
N Div. Value
4
5
10
not used
M/N Div. Value
6.25
5
2.5
Output Frequency (MHz),
(25MHz Ref.)
156.25 (default)
125
62.5
not used
Block Diagram
F_SEL[1:0]
nPLL_SEL
Pulldown
Pulldown
Pin Assignment
2
Q0
nQ1
Q1
V
DDO
Q0
nQ0
MR
nPLL_SEL
nc
V
DDA
F_SEL0
V
DD
F_SEL1
REF_CLK
Pulldown
1
1
XTAL_IN
XTAL_OUT
nXTAL_SEL
25MHz
OSC
0
Phase
Detector
VCO
625MHz
(w/25MHz
Reference)
F_SEL[1:0]
0 0 ÷4 (default)
0 1 ÷5
1 0 ÷10
1 1 not used
nQ0
Q1
nQ1
0
Q2
nQ2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQ2
Q2
V
DDO
Q3
nQ3
GND
nc
nXTAL_SEL
REF_CLK
GND
XTAL_IN
XTAL_OUT
Pulldown
M = 25 (fixed)
Q3
nQ3
MR
Pulldown
ICS844004I-01
24-Lead TSSOP
4.4mm x 7.8mm x 0.92mm
package body
G Package
Top View
ICS844004BGI-01 REVISION A MAY 20, 2013
1
©2013 Integrated Device Technology, Inc.
ICS844004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Table 1. Pin Descriptions
Number
1, 2
3, 22
4, 5
Name
nQ1, Q1
V
DDO
Q0, nQ0
Output
Power
Output
Type
Description
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS/LVTTL interface levels.
PLL select. Selects between the PLL and REF_CLK as input to the dividers.
When LOW, selects PLL (PLL enabled). When HIGH, the PLL is bypassed.
LVCMOS/LVTTL interface levels.
No connect.
Analog supply pin.
Pulldown
Frequency select pins. LVCMOS/LVTTL interface levels.
Core supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
Power supply ground.
Pulldown
Pulldown
Single-ended reference clock input. LVCMOS/LVTTL interface levels.
Selects between crystal or REF_CLK inputs as the PLL reference source.
Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
6
MR
Input
Pulldown
7
8, 18
9
10,
12
11
13,
14
15, 19
16
17
20, 21
23, 24
nPLL_SEL
nc
V
DDA
F_SEL0,
F_SEL1
V
DD
XTAL_OUT,
XTAL_IN
GND
REF_CLK
nXTAL_SEL
nQ3, Q3
Q2, nQ2
Input
Unused
Power
Input
Power
Input
Power
Input
Input
Output
Output
Pulldown
NOTE:
Pulldown
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
Parameter
Input Capacitance
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
ICS844004BGI-01 REVISION A MAY 20, 2013
2
©2013 Integrated Device Technology, Inc.
ICS844004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
10mA
15mA
82.3C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.11
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
64
11
48
Units
V
V
V
mA
mA
mA
Table 3B. Power Supply DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Core Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.11
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
V
DD
2.625
62
11
45
Units
V
V
V
mA
mA
mA
ICS844004BGI-01 REVISION A MAY 20, 2013
3
©2013 Integrated Device Technology, Inc.
ICS844004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
Table 3C. LVCMOS/LVTTL DC Characteristics,
T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
Test Conditions
V
DD
= 3.3V
V
DD
= 2.5V
Input Low Voltage
Input
High Current
Input
Low Current
REF_CLK, MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
REF_CLK, MR, F_SEL[0:1],
nPLL_SEL, nXTAL_SEL
V
DD
= 3.3V
V
DD
= 2.5V
V
DD
= V
IN
= 3.465V or
2.625V
V
DD
= 3.465V or 2.625V,
V
IN
= 0V
-5
Minimum
2
1.7
-0.3
-0.3
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
150
Units
V
V
V
V
µA
µA
V
IL
I
IH
I
IL
Table 3D. LVDS DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.2
Test Conditions
Minimum
247
Typical
Maximum
454
50
1.55
50
Units
mV
mV
V
mV
Table 3E. LVDS DC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
OD
V
OD
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Offset Voltage
V
OS
Magnitude Change
1.1
Test Conditions
Minimum
247
Typical
Maximum
454
50
1.5
50
Units
mV
mV
V
mV
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
NOTE: Characterized using an 18pF parallel resonant crystal.
22.4
Test Conditions
Minimum
Typical
Fundamental
25
27.2
50
7
MHz
Maximum
Units
pF
ICS844004BGI-01 REVISION A MAY 20, 2013
4
©2013 Integrated Device Technology, Inc.
ICS844004I-01 Data Sheet
FEMTOCLOCK™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
AC Electrical Characteristics
Table 5A. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
f
OUT
tsk(o)
tjit(Ø)
t
R
/ t
F
odc
t
LOCK
Parameter
Output Frequency
Output Skew; NOTE 1, 2
156.25MHz, (1.875MHz – 20MHz)
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
125MHz, (1.875MHz – 20MHz)
62.5MHz, (1.875MHz – 20MHz)
20% to 80%
350
48
0.41
0.45
0.45
920
52
100
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
Minimum
Typical
156.25
125
62.5
55
Maximum
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Using 25MHz crystal.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Table 5B. AC Characteristics,
V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
f
OUT
tsk(o)
tjit(Ø)
t
R
/ t
F
odc
t
LOCK
Parameter
Output Frequency
Output Skew; NOTE 1, 2
156.25MHz, (1.875MHz – 20MHz)
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
125MHz, (1.875MHz – 20MHz)
62.5MHz, (1.875MHz – 20MHz)
20% to 80%
330
48
0.41
0.45
0.45
940
52
100
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10
Minimum
Typical
156.25
125
62.5
55
Maximum
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
ms
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Using 25MHz crystal.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross
points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
ICS844004BGI-01 REVISION A MAY 20, 2013
5
©2013 Integrated Device Technology, Inc.
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