®
®
ADS-944
14-Bit, 5MHz
Sampling A/D Converters
FEATURES
•
•
•
•
•
•
•
•
•
14-bit resolution
5MHz minimum sampling rate
No missing codes over full military temperature range
Edge-triggered, no pipeline delay
Low power, 2.95 Watts
Small, 32-pin, ceramic TDIP package
SMT package available
Excellent dynamic performance
MIL-STD-883 screening or DESC SMD available
INPUT/OUTPUT CONNECTIONS
GENERAL DESCRIPTION
The low-cost ADS-944 is a high-performance, 14-bit, 5MHz
sampling A/D converter. This device accurately samples full-
scale input signals up to Nyquist frequencies with no missing
codes. The dynamic performance of the ADS-944 has been
optimized to achieve a THD of –77dB and a SNR of 76dB.
Packaged in a small, 32-pin TDIP, the functionally complete
ADS-944 contains a fast-settling sample-hold amplifier, a
subranging (two-pass) A/D converter, an internal reference,
timing and control logic, three-state outputs, and error-
correction circuitry. Digital input and output levels are TTL.
Requiring ±15V, +5V and –5.2V supplies, the ADS-944
typically dissipates 2.95 Watts. The unit is offered with a
bipolar input range of ±1.25V. Models are available for use in
either commercial (0 to +70°C) or military (–55 to +125°C)
operating temperature ranges. Typical applications include
radar signal analysis, medical/graphic imaging, and
FFT spectrum analysis.
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FUNCTION
+5V ANALOG SUPPLY
–5.2V DIGITAL SUPPLY
ANALOG INPUT
ANALOG GROUND
OFFSET ADJUST
ANALOG GROUND
GAIN ADJUST
COMP. BITS
OUTPUT ENABLE
+5V DIGITAL SUPPLY
ANALOG GROUND
+15V SUPPLY
–15V SUPPLY
–5.2V ANALOG SUPPLY
DIGITAL GROUND
EOC
PIN
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
FUNCTION
START CONVERT
BIT 1 (MSB)
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14 (LSB)
BUFFER
ANALOG INPUT 3
–
S/H
+
FLASH
ADC
1
31 BIT 1 (MSB)
30 BIT 1 (MSB)
29 BIT 2
DIGITAL CORRECTION LOGIC
3-STATE OUTPUT REGISTER
28 BIT 3
27 BIT 4
26 BIT 5
25 BIT 6
24 BIT 7
23 BIT 8
22 BIT 9
21 BIT 10
20 BIT 11
19 BIT 12
18 BIT 13
17 BIT 14 (LSB)
GAIN ADJUST 7
GAIN
CIRCUIT
REF
Σ
DAC
OFFSET ADJUST 5
OFFSET
CIRCUIT
AMP
FLASH
ADC
2
START CONVERT 32
EOC 16
TIMING AND
CONTROL LOGIC
9 OUTPUT ENABLE
1
+5V
ANALOG
SUPPLY
2
–5.2V
DIGITAL
SUPPLY
4, 6, 11
ANALOG
GROUND
10
+5V
DIGITAL
SUPPLY
12
+15V
SUPPLY
14
–5.2V
ANALOG
SUPPLY
15
DIGITAL
GROUND
8
COMP.
BITS
Figure 1. ADS-944 Functional Block Diagram
DATEL, Inc., 11 Cabot Boulevard, Mansfield, MA 02048-1151 (U.S.A.)
•
Tel: (508) 339-3000 Fax: (508) 339-6356
•
For immediate assistance: (800) 233-2765
®
®
ADS-944
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
+15V Supply
(Pins 12)
–15V Supply
(Pin 13)
+5V Supply
(Pins 1, 10)
–5V Supply
(Pin 2, 14)
Digital Input
(Pin 8, 9, 32)
Analog Input
(Pin 3)
Lead Temperature
(10 seconds)
LIMITS
0 to +16
0 to –16
0 to +6
0 to –6
–0.3 to +V
DD
+0.3
–5 to +5
+300
UNITS
Volts
Volts
Volts
Volts
Volts
Volts
°C
PHYSICAL/ENVIRONMENTAL
PARAMETERS
Operating Temp. Range, Case
ADS-944MC
ADS-944MM/883
Thermal Impedance
θjc
θca
Storage Temperature Range
Package Type
Weight
MIN.
0
–55
—
—
–65
TYP.
—
—
7
21
—
MAX.
+70
+125
—
—
+150
UNITS
°C
°C
°C/Watt
°C/Watt
°C
32-pin, metal-sealed, ceramic TDIP or SMT
0.46 ounces (13 grams)
FUNCTIONAL SPECIFICATIONS
(T
A
= +25°C, ±V
CC
= ±15V, +V
DD
= +5V,V
dd
= –5.2V, 5MHz sampling rate, and a minimum 3 minute warmup
unless otherwise specified.)
+25°C
ANALOG INPUT
Input Voltage Range
Input Resistance
Input Capacitance
DIGITAL INPUT
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Start Convert Positive Pulse Width
STATIC PERFORMANCE
Resolution
Integral Nonlinearity
(f
in
= 10kHz)
Differential Nonlinearity
(f
in
= 10kHz)
Full Scale Absolute Accuracy
Bipolar Zero Error
(Tech Note 2)
Bipolar Offset Error
(Tech Note 2)
Gain Error
(Tech Note 2)
No Missing Codes
(f
in
= 10kHz)
DYNAMIC PERFORMANCE
Peak Harmonics
(–0.5dB)
dc to 100kHz
100kHz to 1MHz
1MHz to 2.5MHz
Total Harmonic Distortion
(–0.5dB)
dc to 100kHz
100kHz to 1MHz
1MHz to 2.5MHz
Signal-to-Noise Ratio
(w/o distortion, –0.5dB)
dc to 100kHz
100kHz to 1MHz
1MHz to 2.5MHz
Signal-to-Noise Ratio
(& distortion, –0.5dB)
dc to 100kHz
100kHz to 1MHz
1MHz to 2.5MHz
Noise
Two-tone Intermodulation
Distortion
(f
in
= 2.45MHz,
1.975MHz, f
s
= 5MHz, –0.5dB)
Input Bandwidth
(–3dB)
Small Signal (–20dB input)
Large Signal (–0.5dB input)
Feedthrough Rejection
(f
in
= 2.5MHz)
Slew Rate
Aperture Delay Time
Aperture Uncertainty
—
—
—
—
—
—
73
73
73
71
70
68
—
—
—
—
—
—
—
—
–85
–78
–75
–82
–77
–73
76
76
75
75
73
71
135
–82
20
13
90
±110
+10
3
–77
–71
–70
–76
–70
–68
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
73
73
73
71
69
66
—
—
—
—
—
—
—
—
–85
–78
–75
–82
–77
–73
76
76
75
75
73
71
135
–82
20
13
90
±110
+10
3
–75
–70
–68
–74
–70
–65
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
71
71
71
68
65
62
—
—
—
—
—
—
—
—
–81
–75
–71
–78
–73
–70
75
75
75
73
71
69
135
–82
20
13
90
±110
+10
3
–71
–67
–61
–70
–65
–60
—
—
—
—
—
—
—
—
—
—
—
—
—
—
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
µVrms
dB
MHz
MHz
dB
V/µs
ns
ps rms
—
—
–0.95
—
—
—
—
14
14
±0.75
±0.5
±0.15
±0.1
±0.2
±0.2
—
—
—
+1.2
±0.4
±0.3
±0.4
±0.4
—
—
—
–0.95
—
—
—
—
14
14
±0.75
±0.5
±0.15
±0.1
±0.2
±0.2
—
—
—
+1.2
±0.4
±0.3
±0.4
±0.4
—
—
—
–0.95
—
—
—
—
14
14
±1.0
±0.5
±0.4
±0.3
±0.3
±0.4
—
—
—
+1.5
±0.8
±0.6
±0.9
±1.5
—
Bits
LSB
LSB
%FSR
%FSR
%FSR
%
Bits
+2.0
—
—
—
40
—
—
—
—
80
—
+0.8
+20
–20
—
+2.0
—
—
—
40
—
—
—
—
80
—
+0.8
+20
–20
—
+2.0
—
—
—
40
—
—
—
—
80
—
+0.8
+20
–20
—
Volts
Volts
µA
µA
ns
MIN.
—
500
—
TYP.
±1.25
550
6
MAX.
—
—
15
MIN.
—
500
—
0 to +70°C
TYP.
±1.25
550
6
MAX.
—
—
15
MIN.
—
500
—
–55 to +125°C
TYP.
±1.25
550
6
MAX.
—
—
15
UNITS
Volts
Ω
pF
2
®
®
ADS-944
+25°C
DYNAMIC PERFORMANCE cont.
S/H Acquisition Time
( to ±0.003%FSR, 2.5V step)
Overvoltage Recovery Time
A/D Conversion Rate
DIGITAL OUTPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Delay, Edge of ENABLE
to Output Data Valid/Invalid
Output Coding
POWER REQUIREMENTS
Power Supply Ranges
+15V Supply
–15V Supply
+5V Supply
–5V Supply
Power Supply Currents
+15V Supply
–15V Supply
+5V Supply
–5.2V Supply
Power Dissipation
Power Supply Rejection
+14.25
–14.25
+4.75
–4.95
—
—
—
—
—
—
+15.0
–15.0
+5.0
–5.2
+36
–55
+155
–167
2.95
—
+15.75
–15.75
+5.25
–5.45
+45
–65
+168
–175
3.3
±0.05
+14.25
–14.25
+4.75
–4.95
—
—
—
—
—
—
+15.0
–15.0
+5.0
–5.2
+36
–55
+155
–167
2.95
—
+15.75
–15.75
+5.25
–5.45
+45
–65
+168
–175
3.3
±0.05
+14.25
–14.25
+4.9
–5.1
—
—
—
—
—
—
+15.0
–15.0
+5.0
–5.2
+36
–55
+155
–167
2.95
—
+15.75
–15.75
+5.25
–5.45
+45
–65
+168
–175
3.3
±0.05
Volts
Volts
Volts
Volts
mA
mA
mA
mA
Watts
%FSR/%V
+2.4
—
—
—
—
—
—
—
—
—
—
+0.4
–4
+4
+2.4
—
—
—
—
—
—
—
—
+0.4
–4
+4
+2.4
—
—
—
—
—
—
—
—
+0.4
–4
+4
10
Volts
Volts
mA
mA
ns
MIN.
—
—
5
TYP.
85
200
—
MAX.
90
—
—
MIN.
—
—
5
0 to +70°C
TYP.
85
200
—
MAX.
90
—
—
MIN.
—
—
5
–55 to +125°C
TYP.
85
200
—
MAX.
90
—
—
UNITS
ns
ns
MHz
10
—
—
10
—
—
Offset Binary, Complementary Offset Binary, Two's Complement
Footnotes:
All power supplies should be on before applying a start convert pulse. All
supplies and the clock (start convert pulses) must be present during warmup
periods. The device must be continuously converting during this time.
When COMP. BITS (pin 8) is low, logic loading "0" will be –350µA for this pin.
An 80ns wide start convert pulse is used for all production testing. The start
convert pulse should be between 40 – 80ns or 130 – 160ns to ensure proper
operations. The latter range could be used for those applications requiring less
than a 5MHz sampling rate.
Effective bits is equal to:
(SNR + Distortion) – 1.76 +
20 log
6.02
This is the time required before the A/D output is valid after the analog input is
back within its range.
The minimum supply voltages of +4.9V and –5.1V for ±V
DD
are required for
–55°C operations only. The minimum limits are +4.75V and –4.95V when
operating at +125°C.
Typical +5V and –5.2V current drain breakdowns are as follows:
+5V
Analog
= +85mA
+5V
Digital
= +70mA
+5V
Total
= +155mA
–5.2V
Analog
= –114mA
–5.2V
Digital
= –53mA
–5.2V
Total
= –167mA
Full Scale Amplitude
Actual Input Amplitude
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADS-944
requires careful attention to pc-card layout and power
supply decoupling. The device's analog and digital ground
systems
are not
connected to each other internally. For
optimal performance, tie all ground pins (4, 6, 11, and 15)
directly to a large
analog
ground plane beneath the
package. Bypass all power supplies to ground with 4.7µF
tantalum capacitors in parallel with 0.1µF ceramic capaci-
tors.
It is very important that the bypass capacitors be
located as close to the unit as possible.
Inductors or
ferrite beads can also be used to improve the power supply
filtering. Refer to Figure 4, the ADS-944 Evaluation Board
Schematic, for more details.
2. The ADS-944 achieves its specified accuracies without the
need for external calibration. If required, the device's small
initial offset and gain errors can be reduced to zero using
the adjustment circuitry shown in Figure 2. When using this
circuitry, or any similar offset and gain-calibration hardware,
make adjustments following warmup. To avoid interaction,
always adjust offset before gain.
3. Pin 8 (COMP. BITS) selects the ADS-944's digital output
coding. When a logic "1" is applied to pin 8, the output
coding is complementary offset binary. When pin 8 has a
logic "0" applied, the output coding becomes offset binary.
The MSB output (pin 31) may be used under these condi-
tions to achieve two's complement coding. Pin 8 is TTL-
compatible and can be driven with digital logic for those who
want dynamic control of its function. There is an internal
pull-up resistor on this pin, allowing pin 8 to be either
connected to +5V or left open when a logic "1" is needed.
4. To enable the three-state outputs, apply a logic "0" (low) to
OUTPUT ENABLE (pin 9). To disable, apply a logic "1"
(high) to pin 9.
3
®
®
ADS-944
TECHNICAL NOTES CONT.
5. Applying a start convert pulse while a conversion is in
progress (EOC = logic "1") initiates a new and inaccurate
conversion cycle. Data for the interrupted and subsequent
conversions will be invalid.
6. A passive bandpass filter is used at the input of the A/D for
all production testing.
7. Though the ADS-944's digital outputs are capable of
driving multiple LSTTL or HCT loads, we recommend the
output bits and the EOC line each drive only a single gate.
These gates should be located as close to the unit as
possible. If they can not, 33Ω resistors placed in series
with each output can aid in isolating pc run inductances.
The ADS-944 digital outputs should not be connected
directly to noisy digital busses.
8. Do not enable/disable or complement the output bits during
the conversion process (from the falling edge of START
CONVERT to the falling edge of EOC).
For the ADS-944, offset adjusting is normally accomplished at
the point where the MSB is a 1 and all other output bits are 0's
and the LSB just changes from a 0 to a 1. This digital output
transition ideally occurs when the applied analog input is
+½ LSB (+76.3µV).
Gain adjusting is accomplished when all bits are 1's and the
LSB just changes from a 1 to a 0. This transition ideally
occurs when the analog input is at +full scale minus 1½ LSB's
(+1.249771) .
Note: Due to inherent system noise, the averaging of several
conversions may be needed to accurately adjust both offset
and gain to 1LSB of accuracy.
Zero/Offset Adjust Procedure
1. Apply a train of pulses to the START CONVERT input
(pin 32) so the converter is continuously converting.
2. Apply +76.3µV to the ANALOG INPUT (pin 3).
3. Adjust the offset potentiometer until the output bits are
10 0000 0000 0000 and the LSB flickers between 0 and 1
with pin 8 tied low (offset binary) or between 01 1111 1111
1111 and 01 1111 1111 1110 with pin 8 tied high
(complementary offset binary).
4. Two's complement coding requires using BIT 1 (MSB)
(pin 31). With pin 8 tied low, adjust the trimpot until the
code flickers between 00 0000 0000 0000 and 00 0000
0000 0001.
Gain Adjust Procedure
1. Apply +1.249771V to the ANALOG INPUT (pin 3).
2. Adjust the gain potentiometer until all output bits are 1's and
the LSB flickers between 1 and 0 with pin 8 tied low (offset
binary) or until all bits are 0's and the LSB flickers between
1 and 0 with pin 8 tied high (complementary offset binary).
3. Two's complement coding requires using pin 31. With pin 8
tied low, adjust the gain trimpot until the output code flickers
equally between 01 1111 1111 1110 and 01 1111 1111 1111.
4. To confirm proper operation of the device, vary the applied
input voltage to obtain the output coding listed in Table 1.
31 BIT 1 (MSB)
+
+5V
4.7µF
+
10 DIGITAL
SUPPLY
0.1µF
15
2 DIGITAL
SUPPLY
1 ANALOG
SUPPLY
0.1µF
+
4, 6
ANALOG
14 SUPPLY
12
0.1µF
+
11
START CONVERT 32
COMP. BITS
+15V
20k
Ω
–15V
0.1µF
OFFSET
5 ADJUST
GAIN
ADJUST
7
0.1µF
–15V
2
+15V
20k
Ω
30 BIT 1 (MSB)
29 BIT 2
28 BIT 3
27 BIT 4
26 BIT 5
25 BIT 6
24 BIT 7
23 BIT 8
22 BIT 9
21 BIT 10
20 BIT 11
19 BIT 12
CALIBRATION PROCEDURE
(Refer to Figure 2 and Table 1)
Note: Connect pin 5 to ANALOG GROUND (pin 6) for
operation without zero/offset adjustment. Connect pin 7 to
ANALOG GROUND (pin 6) for operation without gain
adjustment.
Any offset and/or gain calibration procedures should not be
implemented until devices are fully warmed up. To avoid
interaction, offset must be adjusted before gain. The ranges of
adjustment for the circuit in Figure 2 are guaranteed to
compensate for the ADS-944's initial accuracy errors and may
not be able to compensate for additional system errors.
A/D converters are calibrated by positioning their digital
outputs exactly on the transition point between two adjacent
digital output codes. This can be accomplished by connecting
LED's to the digital outputs and adjusting until certain LED's
"flicker" equally between on and off. Other approaches
employ digital comparators or microcontrollers to detect when
the outputs change from one code to the next.
4.7µF
–5.2V
0.1µF
4.7µF
4.7µF
–5.2V
+
0.1µF
+5V
ADS-944
4.7µF
+
+15V
18 BIT 13
17 BIT 14 (LSB)
7 OVERFLOW
16 EOC
9 OUTPUT ENABLE
3 ANALOG INPUT
Figure 2. ADS-944
Connection Diagram
4.7µF
–15V
13
4
®
®
ADS-944
Table 1. Output Coding
OUTPUT CODING
MSB
LSB MSB
00 0000 0000 0000
00 1111 1111 1111
00 1111 1111 1111
01 1111 1111 1111
10 1111 1111 1111
11 0111 1111 1111
11 1111 1111 1110
11 1111 1111 1111
COMP. OFF. BIN.
INPUT RANGE
±1.25V
+1.249847
+0.937500
+0.625000
0.000000
–0.625000
–0.937500
–1.249847
–1.250000
BIPOLAR
SCALE
+FS –1 LSB
+3/4 FS
+1/2FS
0
–1/2FS
–3/4FS
–FS +1 LSB
–FS
MSB
LSB
LSB
11 1111 1111 1111
11 1000 0000 0000
11 0000 0000 0000
10 0000 0000 0000
01 0000 0000 0000
00 1000 0000 0000
00 0000 0000 0001
00 0000 0000 0000
OFF. BINARY
01 1111 1111 1111
01 1000 0000 0000
01 0000 0000 0000
00 0000 0000 0000
11 0000 0000 0000
10 1000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
TWO'S COMP.
TIMING
The ADS-944 is an edge-triggered device. A conversion is
initiated by the rising edge of the start convert pulse and no
additional external timing signals are required. The device
does not employ "pipeline" delays to increase its throughput
rate. It does not require multiple start convert pulses to bring
valid digital data to its output pins.
Approximately 10ns after the rising edge of the start convert
signal, the ADS-944's internal sample-hold amplifier is driven
into the hold mode by the internal S/H control line. After a
35ns delay to allow for S/H output transient settling, the
conversion process begins, and the EOC line (pin 16) is driven
high. The complete A/D conversion requires approximately
150ns. The falling of EOC signals that the conversion is now
complete and digital output data is now valid.
This device actually guarantees that digital output data will be
valid for 10ns prior to the falling edge of EOC. Therefore, EOC
can be used to latch data into external registers that have
appropriate setup times. Any other available timing edges,
including a delayed EOC or the rising edge of the next EOC
pulse, can also be used for this purpose.
The falling edge of the start convert pulse, though irrelevant to
device timing, can cause conversion errors if it occurs at
certain times. Therefore, the recommended start convert
pulse width is between 40 and 80ns or between 130 and
160ns. DATEL performs ADS-944 production testing at the full
5MHz sampling rate using 80ns start convert pulses.
START
CONVERT
N
80ns typ.
THERMAL REQUIREMENTS
All DATEL sampling A/D converters are fully characterized and
specified over operating temperature (case) ranges of 0 to
+70°C and –55 to +125°C. All room-temperature (T
A
= +25°C)
production testing is performed without the use of heat sinks or
forced-air cooling. Thermal impedance figures for each device
are listed in their respective specification tables.
These devices do not normally require heat sinks, however,
standard precautionary design and layout procedures should
be used to ensure devices do not overheat. The ground and
power planes beneath the package, as well as all pcb signal
runs to and from the device, should be as heavy as possible to
help conduct heat away from the package.
Electrically-insulating, thermally-conductive "pads" may be
installed underneath the package. Devices should be
soldered to boards rather than "socketed", and of course,
minimal air flow over the surface can greatly help reduce the
package temperature.
In more severe ambient conditions, the package/junction
temperature of a given device can be reduced dramatically
(typically 35%) by using one of DATEL's HS Series heat sinks.
See Ordering Information for the assigned part number. See
page 1-183 of the DATEL Data Acquisition Components
Catalog for more information on the HS Series. Request
DATEL Application Note AN-8, "Heat Sinks for DIP Data
Converters", or contact DATEL directly, for additional
information.
N+1
10ns typ.
INTERNAL S/H
115ns typ.
Hold
Acquisition Time
90ns max.
Hold
60ns typ., ±10ns
35ns typ.
Conversion Time
EOC
150ns typ., 160ns max.
50ns typ., 60ns max.
OUTPUT
DATA
DATA (N-1) VALID
INVALID
DATA
140ns min., 150ns typ.
DATA N VALID
Note: Scale is approximately 10ns per division.
START CONVERT pulse width: 40 to 80ns or 130 to 160ns.
Figure 3. ADS-944 Timing Diagram
5
嵌入式系统
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