The MCS 51 CHMOS microcontroller products are fabricated on Intel's reliable CHMOS process and are
functionally compatible with the standard MCS 51 HMOS microcontroller products. This technology combines
the high speed and density characteristics of HMOS with the low power attributes of CHMOS. This combina-
tion expands the effectiveness of the powerful MCS 51 microcontroller architecture and instruction set.
Like the MCS 51 HMOS microcontroller versions, the MCS 51 CHMOS microcontroller products have the
following features: 4 Kbytes of EPROM/ROM (87C51/80C51BH respectively); 128 bytes of RAM; 32 I/O lines;
two 16-bit timer/counters; a five-source two-level interrupt structure; a full duplex serial port; and on-chip
oscillator and clock circuitry. In addition, the MCS 51 CHMOS microcontroller products exhibit low operating
power, along with two software selectable modes of reduced activity for further power reductionÐIdle and
Power Down.
The Idle mode freezes the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to
continue functioning. The Power Down mode saves the RAM contents but freezes the oscillator, causing all
other chip functions to be inoperative.
The 87C51 is the EPROM version of the 80C51BH. It contains 4 Kbytes of on-chip program memory that can
be electrically programmed, and can be erased by exposure to ultraviolet light. The 87C51 EPROM array uses
a modified Quick-Pulse Programming algorithm, by which the entire 4 Kbyte array can be programmed in about
12 seconds.
NOTICE:
This datasheet contains information on products in full production. Specifications within this datasheet
are subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.
Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT
INTEL CORPORATION, 2004
June 2004
Order
Number: 270419-008
AUTOMOTIVE 80C31BH/80C51BH/87C51
270419 ±1
Figure 1. MCS 51 Microcontroller
Architectural Block Diagram
2
AUTOMOTIVE 80C31BH/80C51BH/87C51
automotive temperature range option, operational
characteristics are guaranteed over the temperature
range of
-
40
°
C to
+
125
°
C ambient.
The automotive and extended temperature versions
of the MCS 51 microcontroller product families are
available with or without burn-in options as listed in
Table 1.
As shown in Figure 2. temperature, burn-in, and
package options are identified by a one- or two-letter
prefix to the part number.
80C31BH/80C51BH/87C51
PRODUCT OPTIONS
Intel’s extended and automotive temperature range
products are designed to meet the needs of those
applications whose operating requirements exceed
commercial standards.
With the extended temperature range option, opera-
tional characteristics are guaranteed over the tem-
perature range of
-
40
°
C to
+
85
°
C ambient. For the
x
x
x
x
270419 – 2
*
Example:
80C51 indicates an automotive temperature range version of the 80C51 in a PLCC package with 4 Kbyte ROM
program memory.
Figure 2. MCS
®
51 Microcontroller Product Family Nomenclature
Table 1. Temperature Options
Temperature
Classification
Extended
Automotive
Temperature
Designation
T
L
A
B
Operating
Temperature
°
C Ambient
-
40 to
+
85
-
40 to
+
85
-
40 to
+
125
-
40 to
+
125
Burn-In
Options
Standard
Extended
Standard
Extended
3
AUTOMOTIVE 80C31BH/80C51BH/87C51
Diagrams are for pin reference only. Package sizes are not to scale.
270419 ±3
EPROM only
Do not connect reserved pins
Pin (PDIP)
270419 ±4
Pad (PLCC)
Figure 3. Pin Connections
PIN DESCRIPTION
V
CC
:
Supply voltage during normal, Idle, and Power
Down operations.
V
SS
:
Circuit ground.
V
SS1
:
V
SS1
Ð(E PROM PLCC only) secondary
ground. Provided to reduce ground bounce and im-
prove power supply bypassing.
NOTE:
This pin is not a substitute for the V
SS
pin (pin 22).
For ROM and ROMless, pin 1 is reservedÐdo not
connect.
Port 0:
Port 0 is an 8-bit open drain bidirectional I/O
port. As an output port each pin can sink 8 LS TTL
inputs. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance
inputs.
Port 0 is also the multiplexed low-order address and
data bus during accesses to external memory. In this
application it uses strong internal pullups when emit-
ting 1s.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullups are required
during program verification.
Port 1:
Port 1 is an 8-bit bidirectional I/O port with
internal pullups. Port 1 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally being pulled low will source
4
current (I
IL
, on the datasheet) because of the inter-
nal pullups.
Port 1 also receives the low-order address bytes
during EPROM programming and program verifica-
tion.
Port 2:
Port 2 is an 8-bit bidirectional I/O port with
internal pullups. Port 2 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally being pulled low will source
current (I
IL
, on the data sheet) because of the inter-
nal pullups.
Port 2 emits the high-order address byte during
fetches from external Program memory and during
accesses to external Data Memory that use 16-bit
address (MOVX DPTR). In this application it uses
strong internal pullups when emitting 1s.
During accesses to external Data Memory that use
8-bit addresses (MOVX Ri), Port 2 emits the con-
tents of the P2 Special Function Register.
Port 2 also receives some control signals and the
high-order address bits during EPROM programming
and program verification.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with
internal pullups. Port 3 pins that have 1s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally being pulled low will source
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