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ISM64-33A3H1-212.500MHZ

产品描述LVCMOS Output Clock Oscillator,
产品类别无源元件    振荡器   
文件大小100KB,共3页
制造商ILSI
官网地址http://www.ilsiamerica.com
下载文档 详细参数 全文预览

ISM64-33A3H1-212.500MHZ概述

LVCMOS Output Clock Oscillator,

ISM64-33A3H1-212.500MHZ规格参数

参数名称属性值
Objectid7393774267
Reach Compliance Codecompliant
振荡器类型LVCMOS

ISM64-33A3H1-212.500MHZ文档预览

3.2 mm x 5.0 mm Ceramic Package SMD Oscillator,
LVCMOS / LVPECL / LVDS
ISM64 Series
Product Features
Small Surface Mount Package
Fast Sample Delivery
Frequencies to 1500 MHz
Pb Free/ RoHS Compliant
Leadfree Processing
Applications
xDSL
Broadcast video
Wireless Base Stations
Sonet /SDH
WiMAX/WLAN
Server and Storage
Ethernet/LAN/WAN
Optical modules
Clock and data recovery
FPGA/ASIC
Backplanes
GPON
Frequency
LVCMOS
LVPECL
LVDS
Output Level
LVCMOS
LVPECL
LVDS
Duty Cycle
LVCMOS
LVPECL
LVDS
Rise / Fall Time
LVCMOS
LVPECL
LVDS
Output Load
LVCMOS
LVPECL
LVDS
Frequency Stability
Supply Voltage
Current
Phase Jitter (RMS)
At 12kHz to 20 MHz
Operating Temp.
Range
Storage
10 MHz to 250 MHz
10 MHz to 1500 MHz
10 MHz to 1500 MHz
VOH=90% VDD min., VOL=10 % VDD max.
VOH=VDD-1.03V max. (Nom. Load), VOL=VDD-1.6V max. (Nom. Load)
VOD=(Diff. Output) 350mV Typ.
50% ±5% @ 50%VDD
50% ±5% @ 50%*
50% ±5% @ 50%*
3.0 ns max. (90%/10%)*
0.6 ns max. (80%/20%)*
0.6 ns max. (80%/20%)*
15pF
50
to VDD - 2.0 VDC
RL=100
/CL=10pF
See Table Below
3.3 VDC ± 10%, 2.5VDC ± 5%
LVCMOS = 45 mA max., LVPECL = 65 mA max. LVDS = 35 mA max.
0.9 ps typical
See Table Below
-40
C to +100
C
Bypass =0.01 uF
Recommended Pad Layout
Pin
1
2
3
4
5
6
Connection
Enable/Disable or N.C.
Enable/Disable or N.C
Ground
Output
Output or N.C.
V
DD
Dimension Units: mm
Part Number Guide
Package
Input
Voltage
3 = 3.3V
6 = 2.5V
Sample Part Number:
Operating
Temperature
1 = 0 C to +70 C
3 = -20 C to +70 C
2 = -40 C to +85 C
ISM64–31A9H2–155.520
Output
3 = LVCMOS
8 = LVDS
9 = LVPECL
Stability
(in ppm)
F =
20
A =
25
B =
50
Enable / Disable
H = Enable (Pin 1)
K = Enable (Pin 2)
Complimentary
Ouput (Pin 5) **
1 = N.C.
2 = Output
Frequency
ISM64
-155.520 MHz
NOTE: A 0.01 µF bypass capacitor is recommended between V
DD
(pin 6) and GND (pin 3) to minimize power supply noise. * Measured as percent of
waveform. ** Available on LVDS and LVPECL ouput only
.
ILSI America Phone 775-851-8880
Fax 775-851-8882
●email:
e-mail@ilsiamerica.com
www.ilsiamerica.com
Specifications subject to change without notice
Rev: 11/08/13_E
Page 1 of 3
3.2 mm x 5.0 mm Ceramic Package SMD Oscillator,
LVCMOS / LVPECL / LVDS
ISM64 Series
Typical Application:
Pb Free Solder Reflow Profile:
*Units are backward compatible with 240C reflow processes
Package Information:
MSL = N.A. (package does not contain plastic, storage life is
unlimited under normal room conditions).
Termination = e4 (Au over Ni over W base metallization).
Tape and Reel Information:
Quantity per
Reel
A
B
C
D
E
F
1000
16 +/-.3
8 +/-.2
7.5 +/-.2
17.5 +/-1
50 / 60 / 80
180 / 250
ILSI America Phone 775-851-8880
Fax 775-851-8882
●email:
e-mail@ilsiamerica.com
www.ilsiamerica.com
Specifications subject to change without notice
Rev: 11/08/13_E
Page 2 of 3
3.2 mm x 5.0 mm Ceramic Package SMD Oscillator,
LVCMOS / LVPECL / LVDS
ISM64 Series
Environmental Specifications
Thermal Shock
Moisture Resistance
Mechanical Shock
Mechanical Vibration
Resistance to Soldering Heat
Hazardous Substance
Solderability
Terminal Strength
Gross Leak
Fine Leak
Solvent Resistance
MIL-STD-883, Method 1011, Condition A
MIL-STD-883, Method 1004
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 2007, Condition A
J-STD-020C, Table 5-2 Pb-free devices (except 2 cycles max)
Pb-Free / RoHS / Green Compliant
JESD22-B102-D Method 2 (Preconditioning E)
MIL-STD-883, Method 2004, Test Condition D
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 1014, Condition A2, R1=2x10-8 atm cc/s
MIL-STD-202, Method 215
Marking
Line 1: ILSI and Date Code (YWW)
Line 2: Frequency
ILSI America Phone 775-851-8880
Fax 775-851-8882
●email:
e-mail@ilsiamerica.com
www.ilsiamerica.com
Specifications subject to change without notice
Rev: 11/08/13_E
Page 3 of 3
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