Cal-Chip
Introduction
Electronics, Incorporated
Handling
CHV S
ERIES
High Voltage Ceramic Chip Capacitors
Cal-Chip Electronics, Incorporated operates a policy of continuous
development for its ranges of Multilayer Ceramic Capacitors. Our
unique construction process ensures excellent volumetric efficiency
and stability of capacitance with temperature.
High Voltage Chip MLC’s have extended values in the 500V series to
those previously offered, together with
voltage ranges up to 10kV.
Ceramics are dense, hard, brittle and abrasive materials. They are
liable to suffer mechanical damage in the form of chips or cracks, if
improperly handled.
MLC’s should never be handled with metallic instruments.
D
IELECTRIC
C
HARACTERISTICS
Dielectric classification:
Rated temperature range:
Maximum capacitance change
over temperature range
Tangent of loss angle (tan
δ)
COG / NPO
X7R
Y5V & Z5U
Ultra Stable
-55°C to +125°C
0±30ppm/°C
Cr>50pF≤0.0015
Cr≤50pF=0.0015 (15+0.7)
Cr
100GΩ or
1000s
<10pF ±0.25, ±0.5pF
≥10pF
±1, ±2, ±5, ±10%
1.5 x rated volts
1.5 x rated volts
55/125/56
Zero
Stable
-55°C to +125°C
±15%
≤0.025
General Purpose
+10°C to +85°C
+22 to -56%
≤0.030
Insulation resistance (Ri)
Time Constant (Ri X Cr)
(whichever is less)
Capacitance tolerance
Proof
Voltage
500V
≥1kV
100GΩ or
1000s
+5%, ±10%, ±20%
1.5 x rated volts
1.25 x rated volts
55/125/56
1% per time decade
10GΩ or
100s
±20%, -20+80%
1.5 x rated volts
25/085/56
6% per time decade
Climatic category (IEC)
Aging characteristic (Typ.)
S
URFACE
M
OUNT
C
HIP
C
APACITORS
Ordering Information
Example:
Chip Type
Type No/Size Ref
Termination Options
F=Silver Palladium
N=Nickel Barrier
A=High Leach Resistant Silver Palladium
Voltage d.c.
500=500V
1k0=1kV
2k0=2kV
Packaging
T=178mm(7" reel)
Dielectric Code
C=COG, X=X7R, Z=Z5U,
Y=Y5V
Capacitance Tolerance
Code
F=1%
G=2%
J=5%
K=10%
M=20%
Z=20-80%
CHV
3640
N
1k0
103
K
X
T
3k0=3kV
4k0=4kV
5k0=5kV
250=250V
10k0=10kV
Capacitance Code
FPGA/CPLD
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