CAT1320, CAT1321
Supervisory Circuits with I
2
C Serial 32K CMOS EEPROM
FEATURES
s
Precision power supply voltage monitor
s
3.0V to 5.5V operation
s
Low power CMOS technology
s
64-Byte page write buffer
s
1,000,000 Program/Erase cycles
s
100 year data retention
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
— 5V, 3.3V and 3V systems
- +5.0V (+/- 5%, +/- 10%)
- +3.3V (+/- 5%, +/- 10%)
- +3.0V (+/- 10%)
s
Active low reset, CAT1320
s
Active high reset, CAT1321
s
Valid reset guaranteed at V
CC
=1V
s
400kHz I
2
C bus
s
8-pin DIP, SOIC, TSSOP and TDFN packages
s
Industrial temperature range
DESCRIPTION
The CAT1320 and CAT1321 are complete memory and
supervisory solutions for microcontroller-based systems.
A 32kbit serial EEPROM memory and a system power
supervisor with brown-out protection are integrated
together in low power CMOS technology. Memory
interface is via a 400kHz I
2
C bus.
active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive
typically 200 ms after the supply voltage exceeds the reset
threshold level. With both active high and low reset options,
interface to microcontrollers and other ICs is simple. In
addition, the
RESET
(CAT1320) pin can be used as an
input for push-button manual reset capability.
The CAT1320 provides a precision V
CC
sense circuit
and drives an open drain output,
RESET
low whenever The CAT1320/21 memory features a 64-byte page. In
addition, hardware data protection is provided by a V
CC
V
CC
falls below the reset threshold voltage.
sense circuit that prevents writes to memory whenever V
CC
The CAT1321 provides a precision VCC sense circuit falls below the reset threshold or until V
CC
reaches the reset
that drives an open drain output, RESET high whenever threshold during power up.
V
CC
falls below the reset threshold voltage.
Available packages include an 8-pin DIP, SOIC, TSSOP
The power supply monitor and reset circuit protect and 4.9 x 3mm TDFN.
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals become
PIN CONFIGURATION
PDIP (P, L) SOIC (J, W)
A0 1
A1 2
A2 3
VSS 4
A0 1
A1 2
A2 3
VSS 4
CAT1321
TSSOP (U, Y)
A0 1
A1 2
A2 3
VSS 4
CAT1320
8 VCC
7
RESET
6 SCL
5 SDA
TDFN PACKAGE: 4.9MM X 3MM
(RD2, ZD2)
A0
A1
A2
VSS
1
2
3
4
8
7
CAT1320
8 VCC
7
RESET
6 SCL
5 SDA
VCC
RESET
SCL
SDA
CAT1320
6
5
8 VCC
7 RESET
6 SCL
5 SDA
A0 1
A1 2
A2 3
VSS 4
CAT1321
8 VCC
7 RESET
6 SCL
5 SDA
A0
A1
A2
VSS
1
2
3
4
8
7
VCC
RESET
SCL
SDA
CAT1321
6
5
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 20585, Rev. 00
CAT1320, CAT1321
Advance Information
BLOCK DIAGRAM — CAT1320, CAT1321
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SENSE AMPS
SHIFT REGISTERS
Threshold Voltage Options
Part Dash Minimum
Number Threshold
-45
-42
-30
-28
-25
4.50
4.25
3.00
2.85
2.55
Maximum
Threshold
4.75
4.50
3.15
3.00
2.70
SDA
START/STOP
LOGIC
32kbit
EEPROM
XDEC
CONTROL
LOGIC
OPERATING TEMPERATURE RANGE
Industrial
-40˚C to 85˚C
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
RESET Controller
Precision
Vcc Monitor
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
SCL
A0
A1
A2
RESET
(CAT1320)
RESET (CAT1321)
PIN FUNCTIONS
Pin Name
RESET
V
SS
SDA
SCL
RESET
V
CC
Function
Active Low Reset Input/Output (CAT1320)
Ground
Serial Data/Address
Clock Input
Active High Reset Output (CAT1321)
Power Supply
PIN DESCRIPTION
RESET/RESET
RESET:
RESET OUTPUTS
RESET
These are open-drain pins and
RESET
can also be used
as a manual reset trigger input. By forcing a reset condition
on the pin the device will initiate and maintain a reset
condition. The RESET pin must be connected through a
pull-down resistor and the
RESET
pin must be connected
through a pull-up resistor.
SDA:
SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to trans-
fer all data into and out of the device. The SDA pin is an
open drain output and can be wire-ORed with other open
drain or open collector outputs.
SCL:
SERIAL CLOCK
Serial clock input.
A0, A1, A2:
DEVICE ADDRESS INPUTS
When hardwired, up to eight CAT1320/21 devices may
be addressed on a single bus system (refer to Device
Addressing). When the pins are left unconnected, the
default values are zeros.
Doc. No. 25085, Rev. 00
2
Advance Information
CAT1320, CAT1321
Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions
outside of those listed in the operational sections of this specification
is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Note:
(1) Output shorted for no more than one second. No more than
one output shorted at a time.
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias .................... -40°C to +85°C
Storage Temperature ........................ -65°C to +105°C
Voltage on any Pin with
Respect to Ground
(1)
............. -0.5V to +V
CC
+2.0V
V
CC
with Respect to Ground ................ -0.5V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(1)
........................ 100 mA
D.C. OPERATING CHARACTERISTICS
V
CC
= +3.0V to +5.5V and over the recommended temperature conditions unless otherwise specified.
Symbol
I
LI
I
LO
I
CC1
I
CC2
I
SB
V
IL2
V
IH2
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Power Supply Current (Write)
Power Supply Current (Read)
Standby Current
Input Low Voltage
Input High Voltage
Output Low Voltage
(SDA,
RESET
)
Output High Voltage
(RESET)
I
OL
= 3mA
V
CC
= 3.0V
I
OH
= -0.4mA
V
CC
= 3.0V
CAT132x-45
(V
CC
= 5V)
CAT132x-42
(V
CC
= 5V)
V
TH
Reset Threshold
CAT132x-30
(V
CC
= 3.3V)
CAT132x-28
(V
CC
= 3.3V)
CAT132x-25
(V
CC
= 3V)
V
RVALID1
V
RT1
Reset Output Valid V
CC
Voltage
Reset Threshold Hysteresis
Vcc -
0.75
4.50
4.25
3.00
2.85
2.55
1.00
15
4.75
4.50
3.15
3.00
2.70
V
mV
V
Test Conditions
V
IN
= GND to Vcc
V
IN
= GND to Vcc
f
SCL
= 400kHz
V
CC
= 5.5V
f
SCL
= 400kHz
V
CC
= 5.5V
Vcc = 5.5V,
V
IN
= GND or Vcc
-0.5
0.7 x Vcc
Min
-2
-10
Typ
Max
10
10
3
1
40
0.3 x Vcc
Vcc + 0.5
0.4
Units
µA
µA
mA
mA
µA
V
V
V
V
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
2. V
IL
min and V
IH
max are reference values only and are not tested.
3
Doc No. 25085, Rev. 00
CAT1320, CAT1321
Advance Information
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
OUT(1)
C
IN(1)
Test
Output Capacitance
Input Capacitance
Test Conditions
V
OUT
= 0V
V
IN
= 0V
Max
8
6
Units
pF
pF
A.C. CHARACTERISTICS
V
CC
= 3.0V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle
2
Symbol
f
SCL
t
SP1
t
LOW
t
HIGH
t
R1
t
F1
t
HD;STA
t
SU;STA
t
HD;DAT
t
SU;DAT
t
SU;STO
t
AA
t
DH
t
BUF1
t
WC3
Parameter
Clock Frequency
Input Filter Spike
Suppression (SDA, SCL)
Clock Low Period
Clock High Period
SDA and SCL Rise Time
SDA and SCL Fall Time
Start Condition Hold Time
Start Condition Setup Time
(for a Repeated Start)
Data Input Hold Time
Data Input Setup Time
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
Time the Bus must be Free Before a
New Transmission Can Start
Write Cycle Time (Byte or Page)
50
1.3
5
0.6
0.6
0
100
0.6
900
1.3
0.6
300
300
Min
Max
400
100
Units
kHz
ns
µs
µs
ns
ns
µs
µs
ns
ns
µs
ns
ns
µs
ms
Notes:
1. This parameter is characterized initially and after a design or process change that affects
the parameter. Not 100% tested.
2. Test Conditions according to “AC Test Conditions” table.
3. The write cycle time is the time from a valid stop condition of a write sequence to the end of
the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled,
SDA is allowed to remain high and the device does not respond to its slave address.
Doc. No. 25085, Rev. 00
4
Advance Information
CAT1320, CAT1321
RESET CIRCUIT A.C. CHARACTERISTICS
Symbol
t
PURST
t
RPD
t
GLITCH
MR Glitch
t
MRW
Parameter
Reset Timeout
V
TH
to RESET output Delay
V
CC
Glitch Reject Pulse Width
Manual Reset Glitch Immunity
MR Pulse Width
Test
Conditions
Note 2
Note 3
Note 4, 5
Note 5
Note 5
5
Min
130
Typ
200
Max
270
5
30
100
Units
ms
µs
ns
ns
µs
POWER-UP TIMING
5,6
Symbol
t
PUR
t
PUW
Parameter
Power-Up to Read Operation
Power-Up to Write Operation
Test
Conditions
Min
Typ
Max
270
270
Units
ms
ms
Notes:
1. Test Conditions according to “AC Test Conditions” table.
2. Power-up, Input Reference Voltage V
CC
= V
TH
, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
3. Power-Down, Input Reference Voltage V
CC
= V
TH
, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
4. V
CC
Glitch Reference Voltage = V
THmin
; Based on characterization data
5. This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
6. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified memory operation can be initiated.
AC TEST CONDITIONS
Input pulse voltages
Input rise and fall times
Input reference voltages
Output reference voltages
Output Load
0.2V
CC
to 0.8V
CC
10 ns
0.3V
CC
, 0.7V
CC
0.5V
CC
Current Source: I
OL
= 3mA;
C
L
= 100pF
RELIABILITY CHARACTERISTICS
Symbol
N
END(1)
T
DR(1)
V
ZAP(1)
I
LTH(1)(2)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
Min
Max
Units
Cycles/Byte
Years
Volts
mA
MIL-STD-883, Test Method 1033 1,000,000
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
100
2000
100
Notes:
1. This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
2. Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to V
CC
+ 1V.
5
Doc No. 25085, Rev. 00
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