Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MCF54418
Rev. 8, 06/2012
MCF5441x
MAPBGA–256
17mm x 17mm
MAPBGA–196
12 mm x 12 mm
MCF5441x ColdFire
Microprocessor Data Sheet
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Version 4 ColdFire Core with EMAC and
MMU
Up to 385 Dhrystone 2.1 MIPS @ 250 MHz
8 KB instruction cache and 8 KB data cache
64 KB internal SRAM dual-ported to
processor local bus and other crossbar switch
masters
System boot from NOR, NAND, SPI flash,
EEPROM, or FRAM
Crossbar switch technology (XBS) for
concurrent access to peripherals or RAM
from multiple bus masters
64-channel DMA controller
SDRAM controller supporting full-speed
operation from a single x8 DDR2 component
up to 250 MHz
32-bit FlexBus external memory interface for
RAM, ROM, MRAM, and programmable
logic
USB 2.0 host controller
USB 2.0 host/device/On-the-Go controller
8-bit single data rate ULPI port usable by the
dedicated USB host module or the USB
host/device/OTG module
Dual 10/100 Ethernet MACs with hardware
CRC checking/generation, IEEE 1588-2002
support, and optional Ethernet switch
CPU direct-attached hardware accelerator for
DES, 3DES, AES, MD5, SHA-1, and
SHA-256 algorithms
Random number generator
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Enhanced Secure Digital host controller for
SD, SDHC, SDIO, MMC, and MMCplus
cards
Two ISO7816 smart card interfaces
Two FlexCAN modules
Six I
2
C bus interfaces with DMA support in
master mode
Two synchronous serial interfaces
Four 32-bit timers with DMA support
Four programmable interrupt timers
8-channel, 16-bit motor control PWM timer
Dual 12-bit ADCs with shared input channels
and multiple conversion trigger sources
Dual 12-bit DACs with DMA support
1-wire module with DMA support
NAND flash controller
Real-time clock with 32-kHz oscillator, 2 KB
standby SRAM, and battery backup supply
input
Up to four DMA-supported serial peripheral
interfaces (DSPI)
Up to ten UARTs with single-wire mode
support
Up to five external IRQ interrupts and 2
external DMA request/acknowledge pairs
Up to 16 processor local bus Rapid GPIO pins
Up to 87 standard GPIO pins
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2011-2012. All rights reserved.
Table of Contents
1
2
MCF5441x family comparison . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Hardware design considerations . . . . . . . . . . . . . . . . . . . . . . .5
2.1 Power filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.2 Supply voltage sequencing . . . . . . . . . . . . . . . . . . . . . . .7
2.2.1 Power-up sequence . . . . . . . . . . . . . . . . . . . . . . .8
2.2.2 Power-down sequence . . . . . . . . . . . . . . . . . . . .8
2.3 Power consumption specifications . . . . . . . . . . . . . . . . .8
Pin assignments and reset states. . . . . . . . . . . . . . . . . . . . . . .9
3.1 Signal multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.2 Pinout—196 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .19
3.3 Pinout—256 MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . .20
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .21
4.2 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .22
4.3 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.4 Static latch-up (LU) . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.5 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . .23
4.6 Output pad loading and slew rate . . . . . . . . . . . . . . . . .25
4.7 DDR pad drive strengths. . . . . . . . . . . . . . . . . . . . . . . .26
4.8 Oscillator and PLL electrical characteristics . . . . . . . . .26
4.9 Reset timing specifications . . . . . . . . . . . . . . . . . . . . . .28
4.10 FlexBus timing specifications . . . . . . . . . . . . . . . . . . . .28
4.11 NAND flash controller (NFC) timing specifications . . . .30
4.12 DDR SDRAM controller timing specifications . . . . . . . .33
4.13 USB transceiver timing specifications . . . . . . . . . . . . . .35
4.14 ULPI timing specifications. . . . . . . . . . . . . . . . . . . . . . .35
4.15 eSDHC timing specifications. . . . . . . . . . . . . . . . . . . . .36
4.15.1 eSDHC timing specifications . . . . . . . . . . . . . . .37
4.15.2 eSDHC electrical DC characteristics . . . . . . . .
4.16 SIM timing specifications . . . . . . . . . . . . . . . . . . . . . . .
4.16.1 General timing requirements . . . . . . . . . . . . . .
4.16.2 Reset sequence . . . . . . . . . . . . . . . . . . . . . . . .
4.16.3 Power-down sequence . . . . . . . . . . . . . . . . . . .
4.17 SSI timing specifications . . . . . . . . . . . . . . . . . . . . . . .
4.18 12-bit ADC specifications . . . . . . . . . . . . . . . . . . . . . .
4.19 12-bit DAC timing specifications . . . . . . . . . . . . . . . . .
4.20 mcPWM timing specifications . . . . . . . . . . . . . . . . . . .
4.21 I
2
C timing specifications . . . . . . . . . . . . . . . . . . . . . . .
4.22 Ethernet assembly timing specifications . . . . . . . . . . .
4.22.1 Receive signal timing specifications. . . . . . . . .
4.22.2 Transmit signal timing specifications . . . . . . . .
4.22.3 Asynchronous input signal timing
specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22.4 MDIO serial management timing
specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 32-bit timer module timing specifications. . . . . . . . . . .
4.24 DSPI timing specifications . . . . . . . . . . . . . . . . . . . . . .
4.25 SBF timing specifications . . . . . . . . . . . . . . . . . . . . . .
4.26 1-Wire timing specifications. . . . . . . . . . . . . . . . . . . . .
4.27 General purpose I/O timing specifications. . . . . . . . . .
4.28 Rapid general purpose I/O timing specifications . . . . .
4.29 JTAG and boundary scan timing specifications . . . . . .
4.30 Debug AC timing specifications . . . . . . . . . . . . . . . . . .
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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44
45
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52
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56
57
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58
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4
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6
7
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
2
Freescale Semiconductor
MCF5441x
JTAG
Version 4 ColdFire Core
8 KB
Instruction
Cache
8 KB
Data
Cache
PLL
Oscillator
PLL
EMAC
Hardware
Divide
BDM
eDMA
2 Ethernet
Controllers
USB Host
L2 Switch
Serial Boot
Facility
NAND Flash
Controller
CAU
64 KB
SRAM
MMU
RGPIO
USB OTG
eSDHC
Crossbar Switch (XBS)
Peripheral Bus Controller 0
Smart Card
RTC & kHz
Oscillator
2 SSIs
ADC
RNG
2 I
2
Cs
2 DACs
EPORT
2 DSPIs
Peripheral Bus Controller 1
FlexBus
1 Wire
mcPWM
DDR2
Controller
2 DSPIs
4 I
2
Cs
2 FlexCANs
GPIO
6 UARTs
3 INTCs
ADC
BDM
CAU
DAC
DSPI
eDMA
eSDHC
EMAC
EPORT
GPIO
I
2
C
4 UARTs
4 PITs
4 DMA
Timers
Note:
Each of the crossbar switch masters, the FlexBus
and SDRAM controller have access to peripheral
bus controller 0, which is not shown.
INTC
JTAG
mcPWM
PIT
PLL
RGPIO
RNG
RTC
SSI
USB OTG
–
Interrupt controller
– Joint Test Action Group interface
– Motor control pulse width modulator
– Programmable interrupt timers
– Phase locked loop module
– Rapid GPIO
– Random number generator
– Real time clock
– Synchronous serial interface
– Universal Serial Bus On-the-Go controller
– Analog-to-digital converter
– Background debug module
– Cryptography acceleration unit
– Digital-to-analog
– DMA serial peripheral interface
– Enhanced direct memory access module
– Enhanced Secure Digital host controller
– Enhanced multiply-accumulate unit
– Edge port module
– General purpose input/output module
– Inter-Integrated Circuit
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
3
MCF5441x family comparison
1
MCF5441x family comparison
Table 1. MCF5441x family configurations
Module
Version 4 ColdFire core with EMAC (enhanced
multiply-accumulate unit) and MMU (memory
management unit)
Cryptography acceleration unit (CAU)
Core (system) and SDRAM clock
Peripheral clock
(Core clock
2)
External bus (FlexBus) clock
Performance (Dhrystone 2.1 MIPS)
Static RAM (SRAM)
Independent data/instruction cache
USB 2.0 Host controller
USB 2.0 Host/Device/On-the-Go controller
UTMI+ Low Pin Interface (ULPI) for external
high-speed USB PHY
10/100 Mbps Ethernet controller with IEEE 1588
support
Level 2 IEEE 1588-compliant 3-port Ethernet
switch
Enhanced Secure Digital host controller (eSDHC)
Smart card/Subscriber Identity Module (SIM)
UARTs
DSPI
CAN 2.0B controllers
I
2
C
Synchronous serial interface (SSI)
12-bit ADC
12-bit DAC
32-bit DMA timers
Periodic interrupt timers (PIT)
Motor control PWM timer (mcPWM)
64-channel DMA controller
Real-time clock with 2 KB standby RAM and
battery back-up input
DDR2 SDRAM controller
FlexBus external memory controller
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—
1
—
—
6
3
1
4
1
—
—
4
4
—
2
—
2 ports
10
4
2
6
2
2
4
4
8 channel
MCF54410
MCF54415
MCF54416
MCF54417
MCF54418
—
—
up to 250 MHz
up to 125 MHz
up to 100 MHz
up to 385
64 KB
8 KB each
2
—
2 ports
10
4
2
6
2
2
4
4
8 channel
—
2
2 ports
10
4
2
6
2
2
4
4
8 channel
2
2 ports
10
4
2
6
2
2
4
4
8 channel
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
4
Freescale Semiconductor
Hardware design considerations
Table 1. MCF5441x family configurations (continued)
Module
NAND flash controller
1-Wire
®
interface
Serial boot facility
Watchdog timer
Interrupt controllers (INTC)
Edge port module (EPORT)
Rapid GPIO pins
General-purpose I/O (GPIO) pins
JTAG - IEEE
®
1149.1 Test Access Port
Package
MCF54410
3
3 IRQs
9
48
196
MAPBGA
MCF54415
3
5 IRQs
16
87
MCF54416
3
5 IRQs
16
87
256
MAPBGA
MCF54417
3
5 IRQs
16
87
MCF54418
3
5 IRQs
16
87
1.1
Ordering information
Table 2. Orderable part numbers
Freescale Part
Number
MCF54410CMF250
MCF54415CMJ250
MCF54416CMJ250
MCF54417CMJ250
MCF54418CMJ250
Description
MCF54410 Microprocessor
MCF54415 Microprocessor
MCF54416 Microprocessor
256 MAPBGA
MCF54417 Microprocessor
MCF54418 Microprocessor
250 MHz
–40 to +85C
Package
196 MAPBGA
Speed
Temperature
2
2.1
Hardware design considerations
Power filtering
To further enhance noise isolation, an external filter is strongly recommended for the analog V
DD
pins (VDDA_PLL and
VDDA_DAC_ADC). The filter shown in
Figure 1
should be connected between the board 3.3 V (nominal) supply and the
analog pins. The resistor and capacitors should be placed as close to the dedicated analog V
DD
pin as possible. The 10
resistor
in the given filter is required.
MCF5441x ColdFire Microprocessor Data Sheet, Rev. 8
Freescale Semiconductor
5
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