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MAX24287EVKIT: 产品描述kit evaluation for max24287; 产品类别开发板/开发套件/开发工具; 文件大小725KB，共69页; 制造商Maxim(美信半导体); 官网地址https://www.maximintegrated.com/en.html

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MAX24287EVKIT概述

kit evaluation for max24287

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19-5987; Rev 0; 7/11

MAX24287

1Gbps Parallel-to-Serial MII Converter

General Description

The MAX24287 is a flexible, low-cost Ethernet

interface conversion IC. The parallel interface can be

configured for GMII, RGMII, TBI, RTBI, or 10/100 MII,

while the serial interface can be configured for

1.25Gbps SGMII or 1000BASE-X operation. In

SGMII mode, the device interfaces directly to

Ethernet switch ICs, ASIC MACs, and 1000BASE-T

electrical SFP modules. In 1000BASE-X mode, the

device interfaces directly to 1Gbps 1000BASE-X SFP

optical modules. The MAX24287 performs automatic

translation of link speed and duplex autonegotiation

between parallel MII MDIO and the serial interface.

Microprocessor interaction is optional for device

operation. Hardware-configured modes support

SGMII master and 1000BASE-X autonegotiation

without software involvement.

This device is ideal for interfacing single-channel

GMII/MII devices such as microprocessors, FPGAs,

network processors, Ethernet-over-SONET or -PDH

mappers, and TDM-over-packet circuit emulation

devices. The device also provides a convenient

solution to interface such devices with electrical or

optical Ethernet SFP modules.

♦

Highlighted Features

Bidirectional Wire-Speed Ethernet Interface

Conversion

Can Interface Directly to SFP Modules and

SGMII PHY and Switch ICs

Serial Interface Configurable as 1000BASE-X or

SGMII Revision 1.8 (4-, 6-, or 8-Pin)

Parallel Interface Configurable as GMII, RGMII,

TBI, RTBI, or 10/100 MII

Serial Interface Has Clock and Data Recovery

Block (CDR) and Does Not Require a Clock

Input

Translates Link Speed and Duplex Mode

Negotiation Between MDIO and SGMII PCS

♦

Supports 10/100 MII or RGMII Operation with

SGMII Running at the Same Rate

Configurable for 10/100 MII DTE or DCE

Modes (i.e., Connects to PHY or MAC)

Can Also Be Configured as General-Purpose

1:10 SerDes with Optional Comma Alignment

Supports Synchronous Ethernet by Providing

a 25MHz or 125MHz Recovered Clock and

Accepting a Transmit Clock

Can Provide a 125MHz Clock for the MAC to

Use as GTXCLK

Accepts 10MHz, 12.8MHz, 25MHz or 125MHz

Reference Clock

Can Be Pin-Configured at Reset for Many

Common Usage Scenarios

Optional Software Control Through MDIO

Interface

GPIO Pins Can Be Configured as Clocks,

Status Signals and Interrupt Outputs

1.2V Operation with 3.3V I/O

Small, 8mm x 8mm, 68-Pin TQFN Package

Applications

Any System with a Need to Interface a Component

with a Parallel MII Interface (GMII, RGMII, TBI RTBI,

10/100 MII) to a Component with an SGMII or

1000BASE-X Interface

Switches and Routers

Telecom Equipment

♦

Ordering Information

PART

MAX24287ETK+

TEMP RANGE

-40°C to +85°C

PIN-PACKAGE

68 TQFN-EP*

+Denotes

a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

Block Diagram appears on page

Maxim Integrated Products 1

Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple

revisions of any device may be simultaneously available through various sales channels. For information about device

errata, go to:

www.maxim-ic.com/errata.

For pricing, delivery, and ordering information, please contact Maxim Direct at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

_________________________________________________________________________________________________

MAX24287

Table of Contents

6.1

6.2

6.3

6.4

6.5

6.6

APPLICATION EXAMPLES ............................................................................................................. 6

BLOCK DIAGRAM ........................................................................................................................... 7

DETAILED FEATURES ................................................................................................................... 7

ACRONYMS, ABBREVIATIONS, AND GLOSSARY ...................................................................... 8

PIN DESCRIPTIONS ........................................................................................................................ 8

FUNCTIONAL DESCRIPTION ....................................................................................................... 16

ONFIGURATION

URING

ESET

............................................................................................. 16

ENERAL

-P

URPOSE

I/O ................................................................................................................ 17

Receive Recovered Clock Squelch Criteria ......................................................................................... 18

Reset .................................................................................................................................................... 18

Processor Interrupts ............................................................................................................................. 18

MDIO Overview .................................................................................................................................... 19

Examples of MAX24287 and PHY Management Using MDIO ............................................................ 21

6.2.1

6.3.1

6.3.2

6.4.1

6.4.2

ESET AND

ROCESSOR

NTERRUPT

............................................................................................. 18

MDIO I

NTERFACE

......................................................................................................................... 19

ERIAL

NTERFACE

– 1000BASE-X

SGMII ............................................................................... 23

ARALLEL

NTERFACE

– GMII, RGMII, TBI, RTBI, MII .................................................................... 24

GMII Mode ........................................................................................................................................... 24

TBI Mode .............................................................................................................................................. 25

RGMII Mode ......................................................................................................................................... 26

RTBI Mode ........................................................................................................................................... 28

MII Mode .............................................................................................................................................. 29

1000BASE-X Auto-Negotiation ............................................................................................................ 30

SGMII Control Information Transfer ..................................................................................................... 32

GMII, RGMII and MII Serial to Parallel Conversion and Decoding ...................................................... 35

GMII, RGMII and MII Parallel to Serial Conversion and Encoding ...................................................... 35

TBI, RTBI Serial to Parallel Conversion and Decoding ....................................................................... 35

TBI Parallel to Serial Conversion and Encoding .................................................................................. 35

Rate Adaption Buffers, Jumbo Packets and Clock Frequency Differences......................................... 35

RX PLL ................................................................................................................................................. 37

TX PLL ................................................................................................................................................. 37

Input Jitter Tolerance ........................................................................................................................... 37

Output Jitter Generation ....................................................................................................................... 37

TX PLL Jitter Transfer .......................................................................................................................... 37

GPIO Pins as Clock Outputs ................................................................................................................ 38

6.6.1

6.6.2

6.6.3

6.6.4

6.6.5

6.7

6.8

UTO

-N

EGOTIATION

(AN) .............................................................................................................. 30

ATA

ATHS

................................................................................................................................. 35

6.7.1

6.7.2

6.8.1

6.8.2

6.8.3

6.8.4

6.8.5

6.9

IMING

ATHS

............................................................................................................................... 36

6.9.1

6.9.2

6.9.3

6.9.4

6.9.5

6.9.6

6.10

6.10.1

6.10.2

6.10.3

OOPBACKS

............................................................................................................................... 38

Diagnostic Loopback ............................................................................................................................ 38

Terminal Loopback............................................................................................................................... 38

Remote Loopback ................................................................................................................................ 38

6.11

6.12

6.13

7.1

7.2

IAGNOSTIC AND

EST

UNCTIONS

............................................................................................ 39

ATA

ATH

ATENCIES

.............................................................................................................. 39

OARD

ESIGN

ECOMMENDATIONS

.......................................................................................... 39

EGISTER

............................................................................................................................. 41

EGISTER

ESCRIPTIONS

.............................................................................................................. 41

REGISTER DESCRIPTIONS ......................................................................................................... 41

_________________________________________________________________________________________________

MAX24287

7.2.1

7.2.2

7.2.3

7.2.4

7.2.5

7.2.6

7.2.7

7.2.8

7.2.9

7.2.10

7.2.11

7.2.12

7.2.13

7.2.14

7.2.15

7.2.16

7.2.17

BMCR ................................................................................................................................................... 42

BMSR ................................................................................................................................................... 43

ID1 and ID2 .......................................................................................................................................... 44

AN_ADV ............................................................................................................................................... 45

AN_RX ................................................................................................................................................. 45

AN_EXP ............................................................................................................................................... 45

EXT_STAT ........................................................................................................................................... 46

JIT_DIAG ............................................................................................................................................. 46

PCSCR ................................................................................................................................................. 47

GMIICR ................................................................................................................................................ 48

CR ........................................................................................................................................................ 49

IR .......................................................................................................................................................... 50

PAGESEL ............................................................................................................................................ 51

ID .......................................................................................................................................................... 52

GPIOCR1 ............................................................................................................................................. 52

GPIOCR2 ............................................................................................................................................. 52

GPIOSR ............................................................................................................................................... 53

8.1

8.2

8.3

8.4

9.1

9.2

9.3

JTAG AND BOUNDARY SCAN .................................................................................................... 54

JTAG D

ESCRIPTION

...................................................................................................................... 54

JTAG TAP C

ONTROLLER

TATE

ACHINE

ESCRIPTION

............................................................... 54

JTAG I

NSTRUCTION

EGISTER AND

NSTRUCTIONS

........................................................................ 56

JTAG T

EST

EGISTERS

................................................................................................................ 57

ELECTRICAL CHARACTERISTICS .............................................................................................. 58

ECOMMENDED

PERATING

ONDITIONS

...................................................................................... 58

DC E

LECTRICAL

HARACTERISTICS

............................................................................................... 58

CMOS/TTL DC Characteristics ............................................................................................................ 59

SGMII/1000BASE-X DC Characteristics.............................................................................................. 59

REFCLK AC Characteristics ................................................................................................................ 60

SGMII/1000BASE-X Interface Receive AC Characteristics................................................................. 60

SGMII/1000BASE-X Interface Transmit AC Characteristics................................................................ 60

Parallel Interface Receive AC Characteristics ..................................................................................... 61

Parallel Interface Transmit AC Characteristics .................................................................................... 63

MDIO Interface AC Characteristics ...................................................................................................... 65

JTAG Interface AC Characteristics ...................................................................................................... 66

9.2.1

9.2.2

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

9.3.6

9.3.7

AC E

LECTRICAL

HARACTERISTICS

............................................................................................... 60

10.

11.

12.

PIN ASSIGNMENTS ...................................................................................................................... 67

PACKAGE AND THERMAL INFORMATION ................................................................................ 68

DATA SHEET REVISION HISTORY .............................................................................................. 69

_________________________________________________________________________________________________

MAX24287

List of Figures

Figure 2-1. Block Diagram ........................................................................................................................................... 7

Figure 6-1. MDIO Slave State Machine ..................................................................................................................... 20

Figure 6-2. Management Information Flow Options, Case 1,Tri-Mode PHY ............................................................. 21

Figure 6-3. Management Information Flow Options, Case 2, SGMII Switch Chip .................................................... 21

Figure 6-4. Management Information Flow Options, Case 3, 1000BASE-X Interface .............................................. 22

Figure 6-5. Recommended External Components for High-Speed Serial Interface ................................................. 23

Figure 6-6. Auto-Negotiation with a Link Partner over 1000BASE-X ........................................................................ 31

Figure 6-7. 1000BASE-X Auto-Negotiation tx_Config_Reg and rx_Config_Reg Fields ........................................... 31

Figure 6-8. SGMII Control Information Generation, Reception and Acknowledgement............................................ 33

Figure 6-9. SGMII tx_Config_Reg and rx_Config_Reg Fields .................................................................................. 33

Figure 6-10. Timing Path Diagram............................................................................................................................. 36

Figure 6-11. Recommended REFCLK Oscillator Wiring ........................................................................................... 40

Figure 8-1. JTAG Block Diagram ............................................................................................................................... 54

Figure 8-2. JTAG TAP Controller State Machine ...................................................................................................... 56

Figure 9-1. MII/GMII/RGMII/TBI/RTBI Receive Timing Waveforms .......................................................................... 61

Figure 9-2. MII/GMII/RGMII/TBI/RTBI Transmit Timing Waveforms ......................................................................... 63

Figure 9-3. MDIO Interface Timing ............................................................................................................................ 65

Figure 9-4. JTAG Timing Diagram ............................................................................................................................. 66

_________________________________________________________________________________________________

MAX24287

List of Tables

Table 5-1. Pin Type Definitions.................................................................................................................................... 8

Table 5-2. Detailed Pin Descriptions – Global Pins (3 Pins) ....................................................................................... 8

Table 5-3. Detailed Pin Descriptions – MDIO Interface (2 Pins) ................................................................................. 9

Table 5-4. Detailed Pin Descriptions – JTAG Interface (5 pins) .................................................................................. 9

Table 5-5. Detailed Pin Descriptions – GPIO signals (5 dedicated pins, 4 shared pins) ............................................ 9

Table 5-6. Detailed Pin Descriptions – SGMII/1000BASE-X Serial Interface (7 pins) .............................................. 10

Table 5-7. Detailed Pin Descriptions – Parallel Interface (25 pins) ........................................................................... 11

Table 5-8. Detailed Pin Descriptions – Power and Ground Pins (15 pins) ................................................................ 15

Table 6-1. Reset Configuration Pins, 15-Pin Mode (COL=0) .................................................................................... 16

Table 6-2. Parallel Interface Configuration ................................................................................................................ 16

Table 6-3. Reset Configuration Pins, 3-Pin Mode (COL=1) ...................................................................................... 17

Table 6-4. GPO1, GPIO1 and GPIO3 Configuration Options ................................................................................... 17

Table 6-5. GPO2 and GPIO2 Configuration Options................................................................................................. 17

Table 6-6. GPIO4, GPIO5, GPIO6 and GPIO7 Configuration Options ..................................................................... 18

Table 6-7. Parallel Interface Modes ........................................................................................................................... 24

Table 6-8. GMII Parallel Bus Pin Naming .................................................................................................................. 24

Table 6-9. TBI Parallel Bus Pin Naming (Normal Mode} ........................................................................................... 25

Table 6-10. TBI Parallel Bus Pin Naming (One-Clock Mode) ................................................................................... 25

Table 6-11. RGMII Parallel Bus Pin Naming ............................................................................................................. 27

Table 6-12. RTBI Parallel Bus Pin Naming ............................................................................................................... 28

Table 6-13. MII Parallel Bus Pin Naming ................................................................................................................... 29

Table 6-14. AN_ADV 1000BASE-X Auto-Negotiation Ability Advertisement Register (MDIO 4) .............................. 31

Table 6-15. AN_RX 1000BASE-X Auto-negotiation Ability Receive Register (MDIO 5) ........................................... 32

Table 6-16. AN_ADV SGMII Configuration Information Register (MDIO 4) .............................................................. 34

Table 6-17. AN_RX SGMII Configuration Information Receive Register (MDIO 5) .................................................. 34

Table 6-18. Timing Path Muxes – No Loopback ....................................................................................................... 36

Table 6-19. Timing Path Muxes – DLB Loopback ..................................................................................................... 36

Table 6-20. Timing Path Muxes – RLB Loopback ..................................................................................................... 37

Table 6-21. GMII Data Path Latencies ...................................................................................................................... 39

Table 7-1. Register Map ............................................................................................................................................ 41

Table 8-1. JTAG Instruction Codes ........................................................................................................................... 56

Table 8-2. JTAG ID Code .......................................................................................................................................... 57

Table 9-1. Recommended DC Operating Conditions ................................................................................................ 58

Table 9-2. DC Characteristics.................................................................................................................................... 58

Table 9-3. DC Characteristics for Parallel and MDIO Interfaces ............................................................................... 59

Table 9-4. SGMII/1000BASE-X Transmit DC Characteristics ................................................................................... 59

Table 9-5. SGMII/1000BASE-X Receive DC Characteristics .................................................................................... 59

Table 9-6. REFCLK AC Characteristics .................................................................................................................... 60

Table 9-7. 1000BASE-X and SGMII Receive AC Characteristics ............................................................................. 60

Table 9-8. 1000BASE-X and SGMII Receive Jitter Tolerance .................................................................................. 60

Table 9-9. SGMII and 1000BASE-X Transmit AC Characteristics ............................................................................ 60

Table 9-10. 1000BASE-X Transmit Jitter Characteristics.......................................................................................... 60

Table 9-11. GMII and TBI Receive AC Characteristics ............................................................................................. 61

Table 9-12. RGMII-1000 and RTBI Receive AC Characteristics ............................................................................... 62

Table 9-13. RGMII-10/100 Receive AC Characteristics ............................................................................................ 62

Table 9-14. MII–DCE Receive AC Characteristics .................................................................................................... 62

Table 9-15. MII–DTE Receive AC Characteristics .................................................................................................... 63

Table 9-16. GMII, TBI, RGMII-1000 and RTBI Transmit AC Characteristics ............................................................ 63

Table 9-17. RGMII-10/100 Transmit AC Characteristics ........................................................................................... 64

Table 9-18. MII–DCE Transmit AC Characteristics ................................................................................................... 64

Table 9-19. MII–DTE Transmit AC Characteristics ................................................................................................... 64

Table 9-20. MDIO Interface AC Characteristics ........................................................................................................ 65

Table 9-21. JTAG Interface Timing............................................................................................................................ 66

Table 11-1. Package Thermal Properties, Natural Convection ................................................................................. 68

MAX24287EVKIT相似产品对比

	MAX24287EVKIT	MAX24288ETK+	MAX24287ETK+
描述	kit evaluation for max24287	Telecom IC	Interface Circuit, 8 X 8 MM, ROHS COMPLIANT, TQFN-68
是否Rohs认证	-	符合	符合
Reach Compliance Code	-	unknown	compliant
Base Number Matches	-	1	1

MAX24287EVKIT

MAX24287EVKIT在线购买

MAX24287EVKIT概述

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