G -LINK
GLT5160L16
16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM
ADVANCED
F
EATURES
u Single 3.3 V ±0.3 V power supply
u Clock frequency 100 MHz / 125 MHz / 143 MHz/
166 MHz
u Fully synchronous operation referenced to clock rising edge
u Dual bank operation controlled by BA (Bank Address)
u CAS latency- 2 / 3 (programmable)
u Burst length- 1 / 2 / 4 / 8 & Full Page (programmable)
u Burst type- sequential / interleave (programmable)
u Industrial grade available
u Byte control by DQMU and DQML
Column access - random
Auto precharge / All bank precharge controlled by A[10]
Auto refresh and Self refresh
4096 refresh cycles / 64 ms
LVTTL Interface
400-mil, 50-Pin Thin Small Outline Package (TSOP II) with
0.8 mm lead pitch
u 60-Ball, 6.4mmx10.1mm VFBGA package with 0.65mm Ball
pitch & 0.35mm Ball diameter.
u 48-Ball,6mmx8mmx0.95mmVFBGA package with 0.75mm
Ball pitch & 0.3mm ball diameter.
u
u
u
•
u
•
u
u
G
ENERAL
D
ESCRIPTION
The GLT5160L16 is a 2-bank x 524288-word x 16-bit Synchro-
nous DRAM, with LVTTL interface. All inputs and outputs are
referenced to the rising edge of CLK. The GLT5160L16 achieves
very high speed data rate up to 166 MHz, and is suitable for main
memory or graphic memory in computer systems.
SEPT. 2004 (Rev.2.7)
1
G -LINK
F
UNCTIONAL
B
LOCK
D
IAGRAM
A[10:0]
BA
CLK
CKE
CS
RAS
CAS
WE
DQML
DQMU
Control
Signal Buffer
Address Buffer
Mode
Register
Memory Array
Bank #0
I/O Buffer
Memory Array
Bank #1
DQ[15:0]
Clock Buffer
Figure 1. 16M (2-Bank x 524288-Word x 16-Bit) Synchronous DRAM
Signal Description
Signal
CLK
CKE
Type
Input
Input
Description
Master Clock: All other inputs are referenced to the rising edge of CLK.
Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased.
CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
Chip Select: When CS is high, any command means No Operation.
Combination of RAS, CAS, WE defines basic commands.
A[10:0] specify the Row / Column Address in conjunction with BA. The Row Address is specified by A[10:0].
The Column Address is specified by A[7:0]. A[10] is also used to indicate precharge option. When A[10] is
high at a read / write command, an auto precharge is performed. When A[10] is high at a precharge command,
both banks are precharged.
Bank Address: BA is not simply A[11]. BA specifies the bank to which a command is applied. BA must be set
with ACT, PRE, READ, WRITE commands.
Data In and Data out are referenced to the rising edge of CLK.
Lower Din[7:0] Mask / Lower Output[7:0] Disable: When DQML is high in burst write, lower Din[7:0] for the
current cycle is masked. When DQML is high in burst read, lower Dout[7:0] is disabled at the next but one
cycle.
Upper Din[15:8] Mask / Upper Output[15:8] Disable: When DQMU is high in burst write, upper Din(8-15) for
the current cycle is masked. When DQMU is high in burst read, upper Dout[15:8] is disabled at the next but
one cycle.
Power Supply for the memory array and peripheral circuitry.
V
DDQ
and V
SSQ
are supplied to the Output Buffers only.
CS
RAS, CAS, WE
A[10:0]
Input
Input
Input
BA
DQ[15:0]
DQML
Input
Input / Output
Input
DQMU
Input
V
DD
, V
SS
V
DDQ
, V
SSQ
Power Supply
Power Supply
2
G-LINK Technology
SEPT. 2004 (Rev. 2.7)
Control Circuitry
G -LINK
F
UNCTIONAL
D
ESCRIPTION
The GLT5160L16 provides basic functions, bank (row) activate,
burst read / write, bank (row) precharge, and auto / self refresh.
Each command is defined by control signals of RAS, CAS and WE
at CLK rising edge. In addition to 3 signals, CS, CKE and A[10] are
used as chip select, refresh option, and precharge option,
respectively.
To know the detailed definition of commands, please see the com-
mand truth table.
CLK
CS
RAS
CAS
WE
CKE
A[10]
Chip Select: L=select, h=deselect
Com-
Com-
Com-
Refresh option @refresh command
Precharge Option @ precharge or read/write
command
Define Basic Com-
Read (READ) [RAS = H, CAS = L, WE = H]
READ command starts burst read from the active bank indicated by
BA. First output data appears after CAS latency. When A[10] = H at
this command, the bank is deactivated after the burst read (auto-pre-
charge, READA).
Write (WRITE) [RAS = H, CAS =WE = L]
WRITE command starts burst write to the active bank indicated by
BA. Total data length to be written is set by burst length. When
A[10] = H at this command, the bank is deactivated after the burst
write (auto-precharge, WRITEA).
Precharge (PRE)
[RAS = L, CAS = H, WE = L]
PRE command deactivates the active bank indicated by BA. This
command also terminates burst read / write operation. When A[10]
= H at this command, both banks are deactivated (precharge all,
PREA).
Activate (ACT) [RAS = L, CAS = WE = H]
ACT command activates a row in an idle bank indicated by BA.
Auto-Refresh (REFA)
[RAS = CAS = L, WE = CKE = H]
REFA command starts auto-refresh cycle. Refresh address includ-
ing bank address are generated internally. After this command, the
banks are precharged automatically. Any other command should
not be asserted until t
RC
is met.
Command Truth Table
[1]
Command
Deselect
No Operation
Row Address Entry & Bank Activate
Single Bank Precharge
Precharge All Banks
Column Address Entry & Write
Column Address Entry & Write with Auto-Precharge
Column Address Entry & Read
Column Address Entry & Read with Auto-Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
Mnemonic
DESEL
NOP
ACT
PRE
PREA
WRITE
WRITEA
READ
READA
REFA
REFS
REFSX
CKE n-
1
H
H
H
H
H
H
H
H
H
H
H
L
L
Burst Terminate
Mode Register Set
TBST
MRS
H
H
CKE n
X
X
X
X
X
X
X
X
X
H
L
H
H
X
X
CS
H
L
L
L
L
L
L
L
L
L
L
H
L
L
L
RAS
X
H
L
L
L
H
H
H
H
L
L
X
H
H
L
CAS
X
H
H
H
H
L
L
L
L
L
L
X
H
H
L
WE
X
H
H
L
L
L
L
H
H
H
H
X
H
L
L
BA
X
X
V
V
V
V
V
V
V
X
X
X
X
X
X
A[10
]
X
X
V
L
H
L
H
L
H
X
X
X
X
X
L
A[9:
0]
X
X
V
X
X
V
V
V
V
X
X
X
X
X
V
1. H = High Level, L = Low Level, V = Valid, X = Don't Care, n = CLK cycle number
G-LINK Technology
SEPT. 2004 (Rev.2.7)
3
G -LINK
Function Truth Table
[1] [2]
Current State
IDLE
CS
H
L
L
L
L
L
L
L
ROW ACTIVE
H
L
L
L
L
L
L
L
L
READ
H
L
L
L
L
L
L
L
L
WRITE
H
L
L
L
L
L
L
L
L
RAS
X
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
CAS
X
H
H
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
WE
X
H
L
X
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
X
BA
BA, CA, A[10]
BA, RA
BA, A[10]
X
Op-Code, Mode-Add
X
X
BA
BA, CA, A[10]
BA, CA, A[10]
BA, RA
BA, A[10]
X
Op-Code, Mode-Add
X
X
BA
BA, CA, A[10]
BA, CA, A[10]
BA, RA
BA, A[10]
X
Op-Code, Mode-Add
X
X
BA
BA, CA, A[10]
BA, CA, A[10]
BA, RA
BA, A[10]
X
Op-Code, Mode-Add
Address
[3]
Command
DESEL
NOP
TBST
READ / WRITE
ACT
PRE / PREA
REFA
MRS
DESEL
NOP
TBST
READ / READA
WRITE / WRITEA
ACT
PRE / PREA
REFA
MRS
DESEL
NOP
TBST
READ / READA
WRITE / WRITEA
ACT
PRE / PREA
REFA
MRS
DESEL
NOP
TBST
READ / READA
WRITE / WRITEA
ACT
PRE / PREA
REFA
MRS
NOP
NOP
ILLEGAL
[5]
ILLEGAL
[5]
Bank Active, Latch RA
NOP
[6]
Auto-Refresh
[7]
Mode Register Set
[7]
NOP
NOP
NOP
Begin Read, Latch CA, Determine Auto-
Precharge
Begin Write, Latch CA, Determine Auto-
Precharge
Bank Active / ILLEGAL
[5]
Precharge / Precharge All
ILLEGAL
ILLEGAL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
Terminate Burst
Terminate Burst, Latch CA, Begin New
Read, Determine Auto-Precharge
[8]
Terminate Burst, Latch CA, Begin Write,
Determine Auto-Precharge
[8]
Bank Active / ILLEGAL
[5]
Terminate Burst, Precharge
ILLEGAL
ILLEGAL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
Terminate Burst
Terminate Burst, Latch CA, Begin Read,
Determine Auto-Precharge
[8]
Terminate Burst, Latch CA, Begin Write,
Determine Auto-Precharge
[8]
Bank Active / ILLEGAL
[5]
Terminate Burst, Precharge
ILLEGAL
ILLEGAL
Action
[4]
4
G-LINK Technology
SEPT. 2004 (Rev. 2.7)
G -LINK
Function Truth Table
[1] [2]
(Continued)
Current State
READ with AUTO
PRECHARGE
CS
H
L
L
L
L
L
L
L
L
WRITE with AUTO
PRECHARGE
H
L
L
L
L
L
L
L
L
PRE -CHARGING
H
L
L
L
L
L
L
L
ROW ACTIVATING
H
L
L
L
L
L
L
L
WRITE RECOVERING
H
L
L
L
L
L
L
L
RAS
X
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
H
L
L
L
L
CAS
X
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
X
H
H
L
H
H
L
L
X
H
H
L
H
H
L
L
X
H
H
L
H
H
L
L
WE
X
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
H
L
X
H
L
H
L
X
H
L
X
H
L
H
L
X
H
L
X
H
L
H
L
X
X
X
BA, CA, A[10]
BA, CA, A[10]
BA, RA
BA, A[10]
X
Op-Code, Mode-Add
X
X
X
BA, CA, A[10]
BA, CA, A[10]
BA, RA
BA, A[10]
X
Op-Code, Mode-Add
X
X
X
BA, CA, A[10]
BA, RA
BA, A[10]
X
Op-Code, Mode-Add
X
X
X
BA, CA, A[10]
BA, RA
BA, A[10]
X
Op-Code, Mode-Add
X
X
X
BA, CA, A[10]
BA, RA
BA, A[10]
X
Op-Code, Mode-Add
Address
[3]
Command
DESEL
NOP
TBST
READ / READA
WRITE / WRITEA
ACT
PRE / PREA
REFA
MRS
DESEL
NOP
TBST
READ / READA
WRITE / WRITEA
ACT
PRE / PREA
REFA
MRS
DESEL
NOP
TBST
READ / WRITE
ACT
PRE / PREA
REFA
MRS
DESEL
NOP
TBST
READ / WRITE
ACT
PRE / PREA
REFA
MRS
DESEL
NOP
TBST
READ / WRITE
ACT
PRE / PREA
REFA
MRS
Action
[4]
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
ILLEGAL
ILLEGAL
Bank Active / ILLEGAL
[5]
ILLEGAL
[5]
ILLEGAL
ILLEGAL
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
ILLEGAL
ILLEGAL
Bank Active / ILLEGAL
[5]
ILLEGAL
[5]
ILLEGAL
ILLEGAL
NOP (Idle after t
RP
)
NOP (Idle after t
RP
)
ILLEGAL
[5]
ILLEGAL
[5]
ILLEGAL
[5]
NOP
[6]
(Idle after t
RP
)
ILLEGAL
ILLEGAL
NOP (Row Active after t
RCD
)
NOP (Row Active after t
RCD
)
ILLEGAL
[5]
ILLEGAL
[5]
ILLEGAL
[5]
ILLEGAL
[5]
ILLEGAL
ILLEGAL
NOP
NOP
ILLEGAL
[5]
ILLEGAL
[5]
ILLEGAL
[5]
ILLEGAL
[5]
ILLEGAL
ILLEGAL
G-LINK Technology
SEPT. 2004 (Rev.2.7)
5
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