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ZYBO Reference Manual
Revised February 14, 2014
This manual applies to the ZYBO rev. B
Overview
The ZYBO (ZYnq
BOard)
is a feature-rich, ready-to-use, entry-level embedded software and digital circuit
development platform built around the smallest member of the Xilinx Zynq-7000 family, the Z-7010. The Z-7010 is
based on the Xilinx All Programmable System-on-Chip (AP SoC) architecture, which tightly integrates a dual-core
ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array (FPGA) logic. When coupled with the
rich set of multimedia and connectivity peripherals available on the ZYBO, the Zynq Z-7010 can host a whole
system design. The on-board memories, video and audio I/O, dual-role USB, Ethernet, and SD slot will have your
design up-and-ready with no additional hardware needed. Additionally, six Pmod connectors are available to put
any design on an easy growth path.
The Zynq 7010 AP SoC offers the following features:
650Mhz dual-core Cortex-A9 processor
DDR3 memory controller with 8 DMA channels
High-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO
Low-bandwidth peripheral controller: SPI, UART, CAN, I
2
C
Reprogrammable logic equivalent to Artix-7 FPGA
o
4,400 logic slices, each with four 6-input LUTs and 8 flip-flops
o
240 KB of fast block RAM
o
Two clock management tiles, each with a phase-locked loop (PLL) and mixed-mode clock
manager (MMCM)
o
80 DSP slices
o
Internal clock speeds exceeding 450MHz
o
On-chip analog-to-digital converter (XADC)
DOC#: 502-279
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Other product and company names mentioned may be trademarks of their respective owners.
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ZYBO™ FPGA Board Reference Manual
Figure 1. ZYBO Zynq-7000 development board.
ZYNQ XC7Z010-1CLG400C
512MB x32 DDR3 w/ 1050Mbps bandwidth
Dual-role (Source/Sink) HDMI port
16-bits per pixel VGA source port
Trimode (1Gbit/100Mbit/10Mbit) Ethernet PHY
MicroSD slot (supports Linux file system)
OTG USB 2.0 PHY (supports host and device)
External EEPROM (programmed with 48-bit globally
unique EUI-48/64™ compatible identifier)
Audio codec with headphone out, microphone and line
in jacks
128Mb Serial Flash w/ QSPI interface
On-board JTAG programming and UART to USB
converter
GPIO: 6 pushbuttons, 4 slide switches, 5 LEDs
Six Pmod connectors (1 processor-dedicated, 1 dual
analog/digital, 3 high-speed differential, 1 logic-
dedicated)
The ZYBO is compatible with Xilinx’s new high-performance Vivado Design Suite as well as the ISE/EDK toolset.
These toolsets meld FPGA logic design with embedded ARM software development into an easy to use, intuitive
design flow. They can be used for designing systems of any complexity, from a complete operating system running
multiple server applications in tandem, down to a simple bare-metal program that controls some LEDs.
An accessory kit that contains a 5V/2.5A power adapter, a USB A to Micro B cable, an 8GB speed class 10 microSD
card, and a Xilinx voucher for a Vivado Design Suite license will be available to purchase separately off of the
Digilent website in the near future. The Vivado Design Suite license enables use of the Logic Analyzer tools, which
accelerate debug and testing. This license is a 1 year, device-locked license, and will only work with the Z-7010
Zynq part on the ZYBO. After the license expires, any version of Vivado Design Suite that was released during this 1
year period can continue to be used indefinitely.
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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ZYBO™ FPGA Board Reference Manual
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Callout
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Callout
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Component Description
Processor Reset Pushbutton
14
Component Description
Power Switch
Power Select Jumper and battery header
Shared UART/JTAG USB port
MIO LED
MIO Pushbuttons (2)
MIO Pmod
USB OTG Connectors
Logic LEDs (4)
Logic Slide switches (4)
USB OTG Host/Device Select Jumpers
Standard Pmod
High-speed Pmods (3)
Logic Pushbuttons (4)
XADC Pmod
Logic configuration reset Pushbutton
Audio Codec Connectors
Logic Configuration Done LED
Board Power Good LED
JTAG Port for optional external cable
Programming Mode Jumper
Independent JTAG Mode Enable Jumper
PLL Bypass Jumper
VGA connector
microSD connector (Reverse side)
HDMI Sink/Source Connector
Ethernet RJ45 Connector
Power Jack
Table 1. ZYBO Device Diagram.
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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ZYBO™ FPGA Board Reference Manual
1 Power Supplies
The ZYBO can be powered from the Digilent USB-JTAG-UART port (J11), or from an external power supply. Jumper
JP7 (near the power switch) determines which power source is used. There are three valid configurations for this
jumper corresponding to the three powering options: USB, wall wart with barrel jack, and battery pack. There is a
diagram on the board silkscreen indicating all three.
All on-board power supplies are enabled or disabled by the power switch SW4. The power indicator LED (LD11) is
on when all the supply rails reach their nominal voltage. An overview of the power circuit is shown in Fig.2
Power
Jack
(J15)
Power
Switch
(SW4)
R281
VU5V0
VIN
PVIN5
PVIN1-4
1.5A
2.1A
1.2A
0.6A
D13
0.1A
PGOOD
REF
1.25V (III)
3.3V (III)
1.0V (I)
1.5V (III)
1.8V (II)
IC27: ADR127
JP7
J14
Micro-USB
Port (J11)
EN
1.8V (III, analog)
Power-on Reset
Power On
LED (LD11)
IC26: ADP5052
Power Source Select
JP7
J14
USB
WALL
BATTERY
VIN
EN
0.1A
3.3V (IV, analog)
IC6: ADP150
Figure 2. Power circuit overview.
A USB 2.0 port can deliver maximum 0.5A of current according to the specifications. This should provide enough
power for lower complexity designs. An idling blank board consumes around 0.2A from the 5V input supply. As an
example, the standalone lwIP echo server sample project replying to ping requests consumes 0.38A on average.
More demanding applications, including any that drive multiple peripheral boards or other USB devices, might
require more power than the USB port can provide. In this case, power consumption will increase until it’s limited
by the USB host. This limit varies a lot between manufacturers and depends on many factors. When in current
limit, once the voltage rails dip below their nominal value, the Zynq is reset by the Power-on Reset signal and
power consumption returns to its idle value. Also, some applications may need to run without being connected to
a PC’s USB port. In these instances an external power supply or battery pack can be used.
An external power supply (wall wart) can be used by plugging into to the power jack (J15) and setting jumper JP7
to “wall”. The supply must use a coax, center-positive 2.1mm internal-diameter plug, and deliver 4.5VDC to
5.5VDC and at least 2.5A of current (i.e., at least 12.5W of power). Suitable supplies can be purchased from the
Digilent website or through catalog vendors like DigiKey. Power supply voltages above 6VDC might cause
permanent damage.
An external battery pack can be used by connecting the battery’s positive terminal to the center pin of JP7 and the
negative terminal to the pin labeled J14 next to JP7. The external battery pack must be limited to 5.5VDC. The
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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ZYBO™ FPGA Board Reference Manual
minimum voltage of the battery pack depends on the application: if the USB Host (J10) or HDMI Source (J8)
function is used, at least 4.6V need to be provided. In other cases the minimum voltage is 3.6V.
Voltage regulator circuits from Analog Devices create the required 3.3V, 1.8V, 1.5V, and 1.0V supplies from the
main power input. Table 2 provides additional information (typical currents depend strongly on FPGA configuration
and the values provided are typical of medium size/speed designs).
Supply
3.3V
1.0V
1.5V
1.8V
1.8V
3.3V
1.25V
Circuits
FPGA I/O, USB ports, Clocks,
Ethernet, SD slot, Flash, HDMI
FPGA, Ethernet Core
DDR3
FPGA Auxiliary, Ethernet I/O,
USB OTG
XADC Analog
Audio Analog
XADC Precision Reference
Device
IC26#1: ADP5052
IC26#2: ADP5052
IC26#3: ADP5052
IC26#4: ADP5052
IC26#5: ADP5052
IC6: ADP150
IC27: ADR127
Table 2. ZYBO power supplies.
Current (max/typical)
2.5A/0.1A to 1.5A
2.5A/0.2A to 2.1A
1.2A/0.1A to 1.2A
1.2A/0.1A to 0.6A
200mA/20mA
150mA/50mA
5mA/50uA
The supply rails are daisy-chained to follow the Xilinx-recommended start-up sequence. Flicking the power switch
(SW4) will enable the 1.0V rail, which enables the 1.8V digital supply rail, which in turn enables the I/O supply rails
3.3V and 1.5V. The 1.25V reference and 1.8V analog supply ramp together with the 3.3V rail. Once all the channels
of the ADP5052 (IC26) supply reach regulation, the PGOOD signal will assert, enabling the 3.3V audio supply,
lighting up the power LED (LD11), and de-asserting the Power-On Reset signal (PS_POR_B) of the Zynq.
Each power supply uses a soft-start ramp of 1-10ms to limit in-rush current. There is an additional delay of at least
130ms after the power rails reach regulation and before the Power-On Reset signal de-assert to allow for the
PS_CLK (IC22) to stabilize.
2 Zynq AP SoC Architecture
The Zynq AP SoC is divided into two distinct subsystems: The Processing System (PS), and the Programmable Logic
(PL). Figure 3 shows an overview of the Zynq AP SoC architecture, with the PS colored light green and the PL in
yellow. Note that the PCIe Gen2 controller and Multi-gigabit transceivers are not available on the Zynq-7010
device.
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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