19-4571; Rev 0; 4/09
EVALUATION KIT AVAILABLE
+3.3V, Low-Jitter, Precision Clock
Generator with Multiple Outputs
General Description
The MAX3677 is a low-jitter, precision clock generator
optimized for network applications. The device integrates
a crystal oscillator and a phase-locked loop (PLL) to
generate high-frequency clock outputs for Ethernet
applications.
This proprietary PLL design features ultra-low jitter
(0.4psRMS) and excellent power-supply noise rejection
(PSNR), minimizing design risk for network equipment.
The MAX3677 contains seven LVDS outputs and one
LVCMOS output. The output frequency is 125MHz.
Features
♦
Crystal Oscillator Interface: 25MHz
♦
OSC_IN Interface
PLL Enabled: 25MHz
PLL Disabled: 20MHz to 320MHz
♦
Outputs
Seven LVDS Outputs at 125MHz
One LVCMOS Output at 125MHz
♦
Low Phase Jitter
0.4ps
RMS
(12kHz to 20MHz)
0.2ps
RMS
(1.875MHz to 20MHz)
♦
Excellent PSNR: -66dBc at 125MHz with 40mV
P-P
Supply Noise at 100kHz
♦
Operating Temperature Range: 0°C to +70°C
MAX3677
Applications
Ethernet Networking Equipment
Typical Operating Circuit
+3.3V
±5%
Ordering Information
PART
TEMP RANGE
0°C to +70°C
PIN-PACKAGE
32 TQFN-EP*
MAX3677CTJ+
0.1μF
10.5Ω
0.1μF
0.1μF
10μF
V
DDA
0.01μF
V
DD
V
DDO_DIFF
V
DDO_SE
Q0
125MHz
Z
0
= 50Ω
100Ω
ASIC
+Denotes
a lead(Pb)-free/RoHS-compliant package.
*EP
= Exposed pad.
Pin Configuration
TOP VIEW
GND
Q7
V
DDO_SE
V
DDO_DIFF
Q0
Z
0
= 50Ω
125MHz
Z
0
= 50Ω
100Ω
ASIC
Q1
MAX3677
OPEN
OSC_IN
Q1
Q6
Q6
Q5
18
OPEN
OE
Q2
125MHz
Z
0
= 50Ω
100Ω
ASIC
24
V
DD
25
PLL_BP 26
V
DDA
27
100Ω
ASIC
23
22
21
20
19
17
16
15
14
13
OE
RESERVED
Q4
Q4
V
DDO_DIFF
Q3
Q3
GND
Q2
Z
0
= 50Ω
125MHz
Z
0
= 50Ω
Q3
33pF
X_OUT
25MHz
(C
L
= 18pF)
X_IN
27pF
Q4
V
DD
PLL_BP
Q5
Q3
RESERVED 28
OSC_IN 29
MAX3677
Z
0
= 50Ω
125MHz
Z
0
= 50Ω
100Ω
Z
0
= 50Ω
125MHz
Z
0
= 50Ω
100Ω
ASIC
ASIC
Q5
12
11
10
9
8
Q2
Z
0
= 50Ω
Q4
X_IN 30
X_OUT 31
GND 32
1
Q0
2
Q0
3
GND
4
Q1
5
Q1
6
V
DDO_DIFF
7
Q2
+
*EP
Q5
Z
0
= 50Ω
125MHz
Z
0
= 50Ω
100Ω
ASIC
Q6
Q6
Z
0
= 50Ω
THIN QFN
(5mm
×
5mm)
*EXPOSED PAD CONNECTED TO GROUND.
33Ω
GND
Q7
125MHz
Z
0
= 50Ω
ASIC
________________________________________________________________
Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
+3.3V, Low-Jitter, Precision Clock
Generator with Multiple Outputs
MAX3677
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Range at V
DD
, V
DDA
,
V
DDO_SE
, V
DDO_DIFF ................................................
-0.3V to +4.0V
Voltage Range at Q0,
Q0,
Q1,
Q1,
Q2,
Q2,
Q3,
Q3,
Q4,
Q4,
Q5,
Q5,
Q6,
Q6,
Q7,
PLL_BP,
OE, OSC_IN .............................-0.3V to (V
DD
+ 0.3V)
Voltage Range at X_IN ..........................................-0.3V to +1.2V
Voltage Range at X_OUT
.................................
-0.3V to (V
DD
- 0.6V)
Continuous Power Dissipation (T
A
= +70°C)
32-Pin TQFN (derate 34.5mW/°C above +70°C) .......2759mW
Operating Junction Temperature Range ...........-55°C to +150°C
Storage Temperature Range .............................-65°C to +160°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +3.0V to +3.6V, T
A
= 0°C to +70°C, unless otherwise noted. Typical values are at V
DD
= +3.3V, T
A
= +25°C, unless otherwise
noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled,
PLL_BP
= high-Z or high. When PLL is
bypassed,
PLL_BP
= low.) (Note 1)
PARAMETER
Power-Supply Current (Note 2)
SYMBOL
I
DD
PLL enabled
PLL bypassed
CONDITIONS
MIN
TYP
190
175
1.475
0.925
Figure 1
250
400
MAX
256
UNITS
mA
LVDS OUTPUTS (Q0,
Q0,
Q1,
Q1,
Q2,
Q2,
Q3,
Q3,
Q4,
Q4,
Q5,
Q5,
Q6,
Q6)
Output High Voltage
Output Low Voltage
Differential Output Voltage
Amplitude
Change in Magnitude of
Differential Output for
Complementary States
Output Offset Voltage
Change in Magnitude of Output
Offset Voltage for
Complementary States
Differential Output Impedance
Output Current
Clock Output Rise/Fall Time
Output Duty-Cycle Distortion
LVCMOS/LVTTL OUTPUT (Q7)
Output Frequency
Output High Voltage
Output Low Voltage
Output Rise/Fall Time
Output Duty-Cycle Distortion
Output Impedance
R
OUT
V
OH
V
OL
t
r
, t
f
I
OH
= -12mA
I
OL
= 12mA
20% to 80% at 125MHz (Note 5)
PLL enabled
PLL bypassed (Note 4)
0.15
46
45
0.4
50
50
15
2.6
160
V
DD
0.4
0.8
54
55
MHz
V
V
ns
%
t
r
, t
f
Shorted together
Short to ground (Note 3)
20% to 80%, R
L
= 100
PLL enabled
PLL bypassed (Note 4)
100
48
46
V
OH
V
OL
|V
OD
|
V
V
mV
|V
OD
|
V
OS
|V
OS
|
80
105
5
8
200
50
50
1.125
25
1.275
25
140
mV
V
mV
mA
330
52
54
ps
%
2
_______________________________________________________________________________________
+3.3V, Low-Jitter, Precision Clock
Generator with Multiple Outputs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +3.0V to +3.6V, T
A
= 0°C to +70°C, unless otherwise noted. Typical values are at V
DD
= +3.3V, T
A
= +25°C, unless otherwise
noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled,
PLL_BP
= high-Z or high. When PLL is
bypassed,
PLL_BP
= low.) (Note 1)
PARAMETER
Input-Voltage High
Input-Voltage Low
Input High Current
Input Low Current
SYMBOL
V
IH
V
IL
I
IH
I
IL
V
IN
= V
DD
V
IN
= 0
PLL enabled
PLL bypassed
(Note 7)
I
IH
I
IL
C
IN
V
IN
= V
DD
V
IN
= 0
-80
40
50
1.5
625
125
LVDS outputs
LVCMOS output
12kHz to 20MHz,
PLL_BP
= high (Note 8)
Integrated Phase Jitter
Power-Supply Noise Rejection
(Note 10)
Deterministic Jitter Due to
Supply Noise (Note 11)
Nonharmonic and Subharmonic
Spurs
RJ
RMS
12kHz to 20MHz,
PLL_BP
= high-Z
(Note 9)
LVDS outputs
LVCMOS output
LVDS outputs
LVCMOS output
(Note 12)
f
f
f
f
f
f
f
f
f
f
f
f
=
=
=
=
=
>
=
=
=
=
=
>
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
20
20
0.4
0.4
-66
-49
2.5
18
-90
-115
-124
-126
-130
-143
-149
-113
-123
-126
-130
-144
-151
320
160
1.0
ps
RMS
60
20
1.2
-80
25
320
3.6
80
CONDITIONS
MIN
2.0
0
TYP
MAX
V
DD
0.8
80
UNITS
V
V
μA
μA
MAX3677
INPUT SPECIFICATIONS (PLL_BP, OE)
LVCMOS/LVTTL INPUT SPECIFICATIONS (OSC_IN) (Note 6)
Input Clock Frequency
Input Amplitude Range
Input High Current
Input Low Current
Reference Clock Duty Cycle
Input Capacitance
VCO Center Frequency
Output Frequency with PLL
Enabled
Output Frequency with PLL
Disabled
CLOCK OUTPUT AC SPECIFICATIONS
MHz
MHz
MHz
MHz
V
μA
μA
%
pF
PSNR
dBc
ps
P-P
dBc
LVDS Clock Output SSB Phase
Noise (Note 13)
dBc/Hz
LVCMOS Clock Output SSB
Phase Noise (Note 13)
dBc/Hz
_______________________________________________________________________________________
3
+3.3V, Low-Jitter, Precision Clock
Generator with Multiple Outputs
MAX3677
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +3.0V to +3.6V, T
A
= 0°C to +70°C, unless otherwise noted. Typical values are at V
DD
= +3.3V, T
A
= +25°C, unless otherwise
noted. When using X_IN, X_OUT input, no signal is applied at OSC_IN. When PLL is enabled,
PLL_BP
= high-Z or high. When PLL is
bypassed,
PLL_BP
= low.) (Note 1)
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
A series resistor of up to 10.5Ω is allowed between V
DD
and V
DDA
for filtering supply noise when system power-supply tol-
erance is V
DD
= 3.3V ±5%. See Figure 4.
All outputs unloaded.
The current when an LVDS output is shorted to ground is the steady-state current after the detection circuitry has settled. It
is expected that the LVDS output short to ground condition is short-term only.
Measured with OSC_IN input with 50% duty cycle.
Measured with a series resistor of 33Ω to a load capacitance of 3.0pF. See Figure 2.
The OSC_IN input can be DC- or AC-coupled.
Must be within the absolute maximum rating of V
DD
+ 0.3V.
Measured with 25MHz crystal (with OSC_IN left open).
Measured with 25MHz reference clock applied to OSC_IN.
Measured at 125MHz output with 40mV
P-P
sinusoidal signal on the supply at 100kHz. Measured with a 10.5Ω resistor
between V
DD
and V
DDA
.
Parameter calculated based on PSNR.
Measurement includes XTAL oscillator feedthrough, crosstalk, intermodulation spurs, etc.
Measured with 25MHz XTAL oscillator.
4
_______________________________________________________________________________________
+3.3V, Low-Jitter, Precision Clock
Generator with Multiple Outputs
MAX3677
Qx
R
L
= 100Ω
Qx
V
V
OD
Qx
SINGLE-ENDED OUTPUT
Qx
IV
OD
I
V
OH
V
OS
V
OL
Qx - Qx
V
ODP-P
= 2IV
OD
I
DIFFERENTIAL OUTPUT
0
Figure 1. Driver Output Levels
V
CC
800Ω
MAX3677
Q7
33Ω
Z
0
= 50Ω
3pF
800Ω
0.1μF
Z
0
= 50Ω
50Ω
50Ω
OSCILLOSCOPE
Figure 2. LVCMOS Output Measurement Setup
_______________________________________________________________________________________
5
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