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Genesys™ FPGA Board Reference Manual
Revised April 11, 2016
This manual applies to the Genesys rev. C
Overview
The Genesys circuit board is a complete,
ready-to-use digital circuit development
platform based on a Xilinx Virtex 5 LX50T. The
large on-board collection of high-end
peripherals, including Gbit Ethernet, HDMI
Video, 64-bit DDR2 memory array, and audio
and USB ports make the Genesys board an
ideal host for complete digital systems,
including embedded processor designs based
on Xilinx's MicroBlaze. Genesys is compatible
with all Xilinx CAD tools, including ChipScope,
EDK, and the free WebPack, so designs can be
completed at no extra cost.
The Virtex5-LX50T is optimized for high-
performance logic and offers:
Adept USB2
7,200 slices, each containing four 6-
input LUTs and eight flip-flops
1.7Mbits of fast block RAM
12 digital clock managers
six phase-locked loops
48 DSP slices
500MHz+ clock speeds
Digilent port for
JTAG & data
20
4
iMPACT USB2
Xilinx
programming
DDR2
256MByte
132
49
Virtex 5
20
5
StrataFlash
32Mbyte
The Genesys board includes Digilent's newest
Adept USB2 system, which offers device
programming, real-time power supply
monitoring, automated board tests, virtual
I/O, and simplified user-data transfer
facilities. A second USB programming port,
based on the Xilinx programming cable, is also
built into the board.
A comprehensive collection of board support
IP and reference designs, and a large
collection of add-on boards are available on
the Digilent website.
HDMI Video
Up to 1080i
XC5VLX50T
FFG1136C
29
25
AC-97 Audio
Codec
10/100/1000
Ethernet PHY
Basic I/O
LEDs, Buttons,
switches
USB Host
With OTG
23
8
Clock Gen
Programmable
16x2 LCD
Char. Display
11
2
RS-232 Port
UART COM link
High-Speed
Expansion
2x 68-pin VHDCI
80
32
Pmod Port
Expansion
4x 12-pin
DOC#: 502-138
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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Genesys™ FPGA Board Reference Manual
Features include:
Xilinx Virtex 5 LX50T FPGA, 1136-pin BGA package
256Mbyte DDR2 SODIMM with 64-bit wide data
10/100/1000 Ethernet PHY and RS-232 serial port
multiple USB2 ports for programming, data, and hosting
HDMI video up to 1600x1200 and 24-bit color
AC-97 Codec with line-in, line-out, mic, and headphone
real-time power monitors on all power rails
16Mbyte StrataFlash™ for configuration and data storage
Programmable clocks up to 400MHz
112 I/O's routed to expansion connectors
GPIO includes eight LEDs, two buttons, two-axis navigation switch, eight slide switches, and a 16x2 character LCD
ships with a 20W power supply and USB cable
1
Configuration
After power-on, the FPGA on the Genesys board must be configured (or programmed) before it can perform any
functions. A USB-connected PC can configure the board using the JTAG interface anytime power is on, or a file can
be automatically transferred from the StrataFlash ROM at power-on. An on-board "mode" jumper selects which
programming mode will be used.
Both Digilent and Xilinx freely distribute software that can be used to program the FPGA and the Flash ROM.
Configuration files stored in the ROM use the Byte Peripheral Interface (BPI) mode. In BPI UP mode, the FPGA
loads configuration data from the StrataFlash in an ascending direction starting at address 000000. In BPI DOWN
mode, configuration data loads in a descending direction starting at address 03FFFF.
J7
Digilent
Adept
USB
J21
Xilinx
iMPACT
USB
JTAG
Header
J11
JTAG configuration
To
Adept
USB
BPI
configuration
Numonyx
StrataFlash
32Mbytes
PROG_B
DONE
HSWEN
JP8
M0
M1
M2
Mode
Jumper
1
0
JTAG
1
0
BPI
1
0
UP
1
BPI
1
0
DOWN
Virtex 5
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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Genesys™ FPGA Board Reference Manual
Power
Jack
Power
Switch
Digilent Adept
USB Port
Mode Jumper
Power Good LED
JTAG Header
Xilinx iMPACT USB Port
Once transferred, programming files are stored in SRAM-based memory cells within the FPGA. These SRAM cells
define the FPGA's logic functions and circuit connections until they are erased, either by removing power or
asserting the PROG_B input.
FPGA configuration files transferred using the JTAG interface use the .bin and .svf file types, and BPI files use the
.bit, .bin, and .mcs file types. Xilinx's ISE WebPack and EDK software can create .bit, .svf, .bin, or .mcs files from
VHDL, Verilog, or schematic-based source files (EDK is used for MicroBlaze™ embedded processor-based designs).
Digilent's Adept software and Xilinx's iMPACT software can be used to program the Genesys board from a PC's USB
port.
During FPGA programming, a .bit or .svf file is transferred from the PC to the FPGA using the USB-JTAG port. When
programming the ROM, a .bit, .bin, or .mcs file is transferred to the ROM in a two-step process. First, the FPGA is
programmed with a circuit that can transfer data from the USB-JTAG port into the ROM, and then data is
transferred to the ROM via the FPGA circuit (this complexity is hidden and a simple "program ROM" interface is
shown). After the ROM has been programmed, it can automatically configure the FPGA at a subsequent power-on
or reset event if the Mode jumpers are set to the proper BPI mode. A programming file stored in the StrataFlash
ROM will remain until it is overwritten, regardless of power-cycle events.
2
2.1
Adept System
Adept and iMPACT USB Ports
The Genesys board includes two USB peripheral ports – one for Adept software and another for Xilinx's iMPACT
software. Either port can program the FPGA and StrataFlash, but Adept offers a simplified user interface and many
additional features such as automated board test and user-data transfers. The Adept port is also compatible with
iMPACT, if the Digilent Plug-In for Xilinx Tools is installed on the host PC (download it free from the Digilent
website).
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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Genesys™ FPGA Board Reference Manual
Digilent Adept
USB port
Micro-USB
D_P
D_N
Control [11:0]
FIFO DATA [7:0]
See table
See table
Virtex 5
SCK
SDA
CYPRESS
68013A
TMS
TCK
TDO
TDI
FPGA JTAG
programming
port
I
2
C ROM
(VID/PID)
Parallel JTAG data
Xilinx iMPACT
USB port
Micro-USB
I
2
C ROM
(VID/PID)
D_P
D_N
CYPRESS
68013A
SCK
SDA
CPLD
The plug-in automatically translates iMPACT-generated JTAG commands into formats compatible with the Digilent
USB port, providing a seamless programming experience without leaving the Xilinx tool environment. All Xilinx
tools (iMPACT, ChipScope, EDK, etc.) can work with the plug-in, and they can be used in conjunction with Adept
tools (like the power supply monitor).
Adept's high-speed USB2 system can be used to program the FPGA and ROM, run automated board tests, monitor
the four main board power supplies, add PC-based virtual I/O devices (like buttons, switches, and LEDs) to FPGA
designs, and exchange register-based and file-based data with the FPGA. Adept automatically recognizes the
Genesys board and presents a graphical interface with tabs for each of these applications. Adept also includes
public APIs/DLLs so that users can write applications to exchange data with the Genesys board at up to
38Mbytes/sec. The Adept application, an SDK, and reference materials are freely downloadable from the Digilent
website.
The Xilinx USB port is based on the Xilinx USB programming cable. It can be accessed by all Xilinx CAD tools and
iMPACT.
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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Genesys™ FPGA Board Reference Manual
2.2
Programming Interface
To program the Genesys board using Adept, first set up
the board and initialize the software:
plug in and attach the power supply
plug in the USB cable to the PC and to the USB
port on the board
start the Adept software
turn on Genesys' power switch
wait for the FPGA to be recognized.
Use the browse function to associate the desired .bit or
.svf file with the FPGA, and click on the Program button.
The configuration file will be sent to the FPGA, and a
dialog box will indicate whether programming was
successful. The configuration "done" LED will light after
the FPGA has been successfully configured.
Before starting the programming sequence, Adept ensures that any selected configuration file contains the correct
FPGA ID code – this prevents incorrect .bit files from being sent to the FPGA.
In addition to the navigation bar and browse and program buttons, the Config interface provides an Initialize Chain
button, console window, and status bar. The Initialize Chain button is useful if USB communications with the board
have been interrupted. The console window displays current status, and the status bar shows real-time progress
when downloading a configuration file.
2.3
Flash Interface
The Flash programming application allows .bin, .bit, and
.mcs configuration files to be transferred to the on-
board StrataFlash ROM for BPI programming, and
allows user data files to be transferred to/from the
Flash at user-specified addresses.
The configuration tool supports BPI UP and BPI DOWN
programming from any valid ROM file produced by the
Xilinx tools (be sure the mode jumpers are set to BPI
UP/DOWN appropriately, or Genesys will not auto-
configure properly.)
The Read/Write tools allow data to be exchanged
between files on the host PC and specified address
ranges in Flash.
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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