54ACT823 9-Bit D Flip-Flop
September 2003
54ACT823
9-Bit D Flip-Flop
General Description
The ACT823 is a 9-bit buffered register. It features Clock
Enable and Clear which are ideal for parity bus interfacing in
high performance microprogramming systems. The ACT823
offers noninverting outputs and is fully compatible with
AMD’s Am29823.
Features
n
n
n
n
n
Outputs source/sink 24 mA
TRI-STATE outputs for bus interfacing
Inputs and outputs are on opposite sides
ACT823 has TTL-compatible inputs
Standard Microcircuit Drawing (SMD) 5962-9161001
Logic Symbols
IEEE/IEC
10025301
10025302
Pin Names
D
0
–D
8
O
0
–O
8
OE
CLR
CP
EN
Description
Data Inputs
Data Outputs
Output Enable
Clear
Clock Input
Clock Enable
© 2003 National Semiconductor Corporation
DS100253
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54ACT823
Connection Diagrams
Pin Assignment for DIP
and Cerpack
Pin Assignment
for LCC
10025304
10025303
Functional Description
The ACT823 consists of nine D-type edge-triggered flip-
flops. These have TRI-STATE outputs for bus systems orga-
nized with inputs and outputs on opposite sides. The buff-
ered clock (CP) and buffered Output Enable (OE) are
common to all flip-flops. The flip-flops will store the state of
their individual D inputs that meet the setup and hold time
requirements on the LOW-to-HIGH CP transition. With OE
LOW, the contents of the flip-flops are available at the out-
puts. When OE is HIGH, the outputs go to the high imped-
ance state. Operation of the OE input does not affect the
state of the flip-flops. In addition to the Clock and Output
Enable pins, there are Clear (CLR) and Clock Enable (EN)
pins. These devices are ideal for parity bus interfacing in
high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When the EN
is HIGH, the outputs do not change state, regardless of the
data or clock input transitions.
Function Table
Inputs
OE
H
H
H
L
H
L
H
H
L
L
CLR
X
X
L
L
H
H
H
H
H
H
EN
L
L
X
X
H
H
L
L
L
L
CP
N
N
X
X
X
X
N
N
N
N
D
L
H
X
X
X
X
L
H
L
H
Internal
Q
L
H
L
L
NC
NC
L
H
L
H
Output
O
Z
Z
Z
L
Z
NC
Z
Z
L
H
High Z
High Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
Function
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N = LOW-to-HIGH Transition
NC = No Change
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2
54ACT823
Logic Diagram
10025305
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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54ACT823
Absolute Maximum Ratings
(Note 1)
CDIP
175˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
DC Input Diode Current (I
IK
)
V
I
= −0.5V
V
I
= V
CC
+ 0.5V
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
V
O
= −0.5V
V
O
= V
CC
+ 0.5V
DC Output Voltage (V
O
)
DC Output Source or Sink
Current
(I
O
)
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
−20 mA
+20 mA
−0.5V to V
CC
+ 0.5V
−0.5V to 7.0V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
ACT
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
54ACT
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
125 mV/ns
−55˚C to +125˚C
4.5V to 5.5V
0V to V
CC
0V to V
CC
±
50 mA
±
50 mA
−65˚C to +150˚C
Note 1:
Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
™
circuits outside databook specifications.
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
V
OL
I
IN
I
OZ
I
CCT
I
OLD
I
OHD
I
CC
Parameter
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
Maximum Low Level
Output Voltage
Maximum Input Leakage
Current
Maximum TRI-STATE
Current
Maximum I
CC
/Input
(Note 3) Minimum
Dynamic Output
Current
Maximum Quiescent
Supply Current
Note 2:
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
V
CC
(V)
4.5
5.5
4.5
4.5
4.5
4.5
T
A
=
−55˚C to +125˚C
2.0
2.0
0.8
0.8
3.7
0.5
Units
V
V
Conditions
V
OUT
= 0.1V
or V
CC
−0.1V
V
OUT
= 0.1V
or V
CC
−0.1V
I
OH
= −24 mA
I
OL
= 24 mA
V
V
µA
µA
mA
mA
mA
µA
5.5
5.5
5.5
5.5
5.5
5.5
±
1.0
±
10.0
1.6
50
−50
160
V
I
= V
CC
, GND
V
I
= V
IL
, V
IH
V
O
= V
CC
, GND
V
I
= V
CC
−2.1V
V
OLD
= 1.65V Max
V
OHD
= 3.85V Min
V
IN
= V
CC
or GND
AC Electrical Characteristics
Symbol
Parameter
V
CC
(V)
(Note 4)
5.0
T
A
= −55˚C to +125˚C
C
L
= 50 pF
Min
f
max
Maximum Clock
Frequency
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4
Units
Fig.
No.
Max
MHz
95
54ACT823
AC Electrical Characteristics
Symbol
Parameter
(Continued)
T
A
= −55˚C to +125˚C
C
L
= 50 pF
Min
Max
12.0
12.0
18.0
11.5
12.0
13.5
12.0
ns
ns
ns
ns
ns
ns
ns
Units
Fig.
No.
V
CC
(V)
(Note 4)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
t
PLH
t
PHL
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation Delay
CP to O
n
Propagation Delay
CP to O
n
Propagation Delay
CLR to O
n
Output Enable Time
OE to O
n
Output Enable Time
OE to O
n
Output Disable Time
OE to O
n
Output Disable Time
OE to O
n
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Note 4:
Voltage Range 5.0 is 5.0V
±
0.5V
AC Operating Requirements
Symbol
Parameter
V
CC
(V)
(Note 5)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
T
A
= −55˚C to +125˚C
C
L
= 50 pF
Guaranteed Minimum
t
s
t
h
t
s
t
h
t
w
t
w
t
rec
Setup Time, HIGH or LOW
D to CP
Hold Time, HIGH or LOW
D
n
to CP
Setup Time, HIGH or LOW
EN to CP
Hold Time, HIGH or LOW
EN to CP
CP Pulse Width
HIGH or LOW
CLR Pulse Width, LOW
CLR to CP
Recovery Time
Note 5:
Voltage Range 5.0 is 5.0V
±
0.5V
Units
Fig.
4.0
3.0
4.0
3.0
6.0
7.5
4.5
ns
ns
ns
ns
ns
ns
ns
Capacitance
Symbol
C
IN
C
PD
Parameter
Input Capacitance
Power Dissipation
Capacitance
Max
4.5
4.4
Units
pF
pF
Conditions
V
CC
= OPEN
V
CC
= 5.0V
5
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