IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS
OCTAL D FLIP-FLOP
WITH MASTER RESET
FEATURES:
•
•
•
•
Std., A, and C grades
Low input and output leakage
≤
1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Power off disable outputs permit "live insertion"
Available in the following packages:
– Industrial: SOIC, SSOP, QSOP
– Military: CERDIP, LCC
IDT54/74FCT273T/AT/CT
DESCRIPTION:
The FCT273T is an octal D flip-flop built using an advanced dual metal
CMOS technology. The FCT273T has eight edge-triggered D-type flip-
flops with individual D inputs and O outputs. The common buffered Clock
(CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one set-
up time before the low-to-high clock transition, is transferred to the corre-
sponding flip-flop’s O output.
All outputs will be forced low independently of Clock or Data inputs by
a low voltage level on the
MR
input. The device is useful for applications
where the true output only is required and the Clock and Master Reset are
common to all storage elements.
•
•
•
•
•
FUNCTIONAL BLOCK DIAGRAM
D
0
CP
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
CP
R
D
MR
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
JUNE 2002
DSC-2568/4
© 2002 Integrated Device Technology, Inc.
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
O
0
MR
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
D
0
3
2
1
20
19
18
17
16
15
14
D
1
O
1
O
2
D
2
D
3
O
7
INDEX
MR
V
CC
4
5
6
7
8
9
10
D
7
D
6
O
6
O
5
D
5
11
12
13
GND
CP
O
3
CERDIP/ SOIC/ SSOP/ QSOP
TOP VIEW
LCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(3)
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
V
TERM
(2)
Terminal Voltage with Respect to GND
PIN DESCRIPTION
Pin Names
Dx
MR
CP
Ox
Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
Description
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
FUNCTION TABLE
(1)
Operating Mode
Reset (Clear)
Load "1"
Load "0"
MR
L
L
H
Inputs
CP
X
↑
↑
Dx
X
h
l
Outputs
Ox
L
H
L
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
Input Capacitance
Output Capacitance
NOTE:
1. This parameter is measured at characterization but not tested.
NOTE:
1. H = HIGH voltage level steady state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don’t Care
↑
= LOW-to-HIGH Clock Transition
2
O
4
D
4
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V ±10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
I
V
IK
I
OS
V
OH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min., I
IN
= –18mA
V
CC
= Max., V
O
= GND
(3)
V
CC
= Min
V
IN
= V
IH
or V
IL
I
OH
= –6mA MIL
I
OH
= –8mA IND
I
OH
= –12mA MIL
I
OH
= –15mA IND
I
OL
= 32mA MIL
I
OL
= 48mA IND
—
V
CC
= Max.
V
IN
= GND or V
CC
V
I
= 2.7V
V
I
= 0.5V
Min.
2
—
—
—
—
—
–60
2.4
2
—
—
—
Typ.
(2)
—
—
—
—
—
–0.7
–120
3.3
3
0.3
200
0.01
Max.
—
0.8
±1
±1
±1
–1.2
–225
—
—
0.5
—
1
V
mV
mA
µA
V
mA
V
Unit
V
V
µA
V
OL
V
H
I
CC
Output LOW Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min
V
IN
= V
IH
or V
IL
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at T
A
= –55°C.
3
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
ΔI
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
MR
= V
CC
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
MR
= V
CC
One Bit Toggling
fi = 5MHz
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
MR
= V
CC
Eight Bits Toggling
fi = 2.5MHz
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
0.15
Max.
2
0.25
Unit
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
—
1.5
3.5
mA
V
IN
= 3.4V
V
IN
= GND
—
2
5.5
V
IN
= V
CC
V
IN
= GND
—
3.8
7.3
(5)
V
IN
= 3.4V
V
IN
= GND
—
6
16.3
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input; (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
ΔI
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
ΔI
CC
D
H
N
T
+ I
CCD
(f
CP
/2+ f
i
N
i
)
I
CC
= Quiescent Current
ΔI
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Output Frequency
N
i
= Number of Outputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
4
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
SU
t
H
t
W
t
W
t
REM
Parameter
Propagation Delay
CP to Ox
Propagation Delay
MR
to Ox
Set-up Time HIGH or LOW
Dx to CP
Hold Time HIGH or LOW
Dx to CP
CP Pulse Width HIGH or LOW
MR
Pulse Width LOW
Recovery Time
MR
to CP
Condition
C
L
= 50pF
R
L
= 500Ω
(1)
74FCT273AT
Min.
(2)
Max.
2
7.2
2
2
1.5
6
6
2
7.2
—
—
—
—
—
74FCT273CT
Min.
(2)
Max.
2
5.8
2
2
1.5
6
6
2
6.1
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - MILITARY
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
SU
t
H
t
W
t
W
t
REM
Parameter
Propagation Delay
CP to Ox
Propagation Delay
MR
to Ox
Set-up Time HIGH or LOW
Dx to CP
Hold Time HIGH or LOW
Dx to CP
CP Pulse Width HIGH or LOW
MR
Pulse Width LOW
Recovery Time
MR
to CP
Condition
C
L
= 50pF
R
L
= 500Ω
(1)
54FCT273T
Min.
(2)
Max.
2
15
2
3.5
2
7
7
5
15
—
—
—
—
—
54FCT273AT
Min.
(2)
Max.
2
8.3
2
2
1.5
6
6
2.5
8.3
—
—
—
—
—
54FCT273CT
Min.
(2)
Max.
2
6.5
2
2
1.5
6
6
2.5
6.8
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
5
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