TM
No. AN9517
August 1995
Application Note
Author: Juan C. Garcia
Using the HI5714 Evaluation Board
Features
• HI5714 Analog to Digital Converter
• External Reference
• Two Analog Inputs: One AC Coupled, One DC Coupled
• Reconstruct DAC: HI5721
• Buffered Digital Outputs
V
A
V
IN
V
B
V
1
Assuming no interpolation were to be performed, the number
of folding amplifiers necessary to implement an 8-bit conver-
sion (using a folding ratio of 16) would be DC at 16.
V
CC
V
2
V
3
Description
The HI5714 evaluation board was designed to easily allow a
user to evaluate the performance of the HI5714 8-bit
75 MSPS Analog-to-Digital converter (ADC). The board
includes clock driver circuitry, reference voltage generators,
two input options and a reconstruct DAC. A block diagram of
the evaluation board is shown in Figure 3.
FIGURE 1. FOLDING AMPLIFIER WITH A FOLDING RATIO OF 2
HI5714 Theory of Operation
The HI5714 design utilizes a folding and interpolating archi-
tecture. This architecture reduces the number of compara-
tors, reference taps, and latches in comparison to a full
parallel flash converter, and as a result reduces power
requirements, die size and cost. A full parallel 8-bit flash con-
verter requires 255 comparators, 255 references and 255
latches, while the HI5714 utilizes only 16 comparators, 16
references and 16 latches.
A folding A/D converter operates basically like a 2 step
subranging converter by using 2 lower resolution converters
to do a course and subranged fine conversion. The major
difference in the folding technique is that the folding
amplifiers are used to do the fine conversion in parallel
with the course conversion, where the fine and course
conversions are done in a sequential mode for a
conventional subranging converter. The folding architecture
uses only the folding amplifiers, voltage comparators, flip-
flops and decoding circuits. Sample and hold and DAC
circuits are not required.
A folding amplifier is a number of parallel differential pairs
with interconnected outputs as shown in Figure 1. The fold-
ing ratio is the number of differential pairs used in the ampli-
fier, which is 16 for the HI5714. When compared to a
traditional straight flash architecture, one folding amplifier
with a folding ratio of 16 replaces 16 input comparators.
The interpolation technique further reduces the number of
necessary amplifiers by using passive elements to derive the
remaining signals. Interpolation (as seen in Figure 2) takes
advantage of the overlap between two adjacent amplifiers
and uses resistor taps to fill in the gaps (thereby replacing
three out of every four amplifiers with resistors). Signal dis-
tortion introduced by interpolation can be ignored as only the
zero crossing is of importance.
V
O
0
V
IN
V
2
V
3
V
4
V
01
V
02
FIGURE 2. INTERPOLATED AMPLIFIER OUTPUTS
As stated earlier in this section, the HI5714 uses a folding
ratio of 16 (16 latched comparators) with an interpolation
ratio of 4 (4 folding amplifiers). These 16 latched compara-
tors in turn are decoded into 32 ROM enables to provide the
5 LSBs of the converter. There are 8 subranging sections of
the input voltage range which perform the coarse conversion
and provide the 3 MSBs of the device.
The bias current generator is based on a simple band gap
reference which provides a typical variation of 1% over the
full temperature range.
The operation of the part is depicted in the timing diagram in
Figure 4. There is a 1 cycle clock delay from the analog input
sampling point to the corresponding digital output data.
|
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1
Application Note 9517
CLK
1.2V REF
3.6V
V
RT
1.3V
V
RB
ANALOG
IN1 (DC)
V
IN
ANALOG
IN2 (AC)
+5VA
CE
+5VD +5VA -5VA +12V -12V
DAC
CE
O/UF
8
DOUT
HI5714
26 PIN
CONNECTOR
CLK
FIGURE 3. EVALUATION BOARD BLOCK DIAGRAM
t
CPL
t
CPH
CLOCK
INPUT
1.4V
SAMPLE N
SAMPLE N+1
SAMPLE N+2
ANALOG
INPUT
t
DS
t
HD
2.4V
1.4V
0.4V
DATA (D0-D7)
OUTPUTS
D
N-2
D
N-1
t
D
D
N
D
N+1
FIGURE 4. HI5714 TIMING
Power Supplies and Layout
The HI5714 Evaluation Board is a four layer board with a
layout optimized for the best performance for the ADC. Fig-
ures 11 through 16 include a schematic of the board, a board
layout, and the various board layers. The user should feel
free to copy the layout in their application.
In order optimize the performance of the HI5714 at power
up, it is necessary that AV
DD
and DV
DD
be driven from
separate supplies. The supplies to the board should be
driven by clean linear regulated supplies. They can be
hooked up with external 16 gauge wires to the holes marked
+12V, -12V, +5VA, +5VD, -5.2VA, AGND and DGND on the
prototype area. AGND and DGND are tied together under
the HI5714. Do not tie the supply grounds together back at
the supplies as this will create a ground loop and generate
additional noise.
Decoupling capacitors should be placed as close to the
HI5714 as possible. A 0.1µF and a 0.001µF leaded capacitor
will provide good decoupling but chip capacitors will provide
better decoupling at higher clock frequencies. Do not forget
a large value cap (1µF to 10µF) for low frequency decou-
pling somewhere on your PC board.
2
Application Note 9517
Table 1 lists the operating conditions for the power supplies.
TABLE 1. POWER SUPPLIES
POWER
SUPPLY
+5VA
-5.2VA
+5VD
+12V
-12V
CURRENT
TYP
25mA
-120mA
20mA
25mA
-20mA
Increased Accuracy
Further calibration of the ADC can be done when using the
external reference and input buffer circuit. First, a precision
voltage equal to the ideal V
IN-FS
+ 0.5 LSB is applied at V
IN1
.
R1 is then adjusted until the 0 to 1 transition occurs on the
digital output. Finally, a voltage equal to the ideal V
IN+FS
-
1.5 LSB is applied at V
IN1
. R2 is then adjusted until the 254
to 255 transition occurs on the digital output.
MIN
+4.75V
-5.3V
+4.75V
+10V
-10V
TYP
+5.0V
-5.2V
+5.0V
+12V
-12V
MAX
+5.25V
-5.0V
+5.25V
+15V
-15V
Input Clock Driver and Timing
The clock input to the HI5174 evaluation board should be
driven with a standard TTL level signal. U4 (75F04) will
buffer the clock input and drive the HI5714 as well as the 26
pin connector. For optimum performance of the HI5714 the
duty cycle of the clock should be kept at 50%
±10%.
U5 and
U6 (74F541) will buffer the output bits and keep the power
transients caused by charging a large bus capacitance off
the supplies to the ADC.
As with any high speed ADC, clock jitter (in this case
external) must be accounted for. Clock jitter will cause the
converter to sample at a nonuniform rate, thus having the
effect of distorting the digital representation and raise the
noise floor. For this reason, users should take care to
provide as uniform a clock signal as possible to assure
optimal performance.
TABLE 2. TIMING SPECIFICATIONS
PARAMETER
t
OD
t
PD1
t
PD2
t
PD3
DESCRIPTION
HI5714 Data Delay
74F04 Prop Delay
74F04 Prop Delay
74F541 Prop Delay
MIN
-
2.4ns
2.4ns
2.1ns
TYP
10ns
-
-
-
MAX
13ns
8.5ns
8.5ns
7.5ns
Reference Circuit
For the following discussion, refer to the board schematic
and the board layout drawing.
The HI5714 requires two reference voltages: V
RT
and V
RB
.
The external voltage reference generator on the evaluation
board is used to generate a V
RT
of about 3.6V and a V
RB
of
about 1.3V. The ICL8069 reference diode generates a 1.2V
voltage that is gained up by two op amps to the reference
voltages V
RT
and V
RT
for the ADC. V
RT
should be kept in the
range of 3.2V to 3.6V. P1 is adjusted at the factory for a V
RB
of 1.3V
±2mV.
Then P2 is adjusted for a V
RT
reference volt-
age of +3.6V
±
2mV.
Analog Input
The analog input to the HI5174 can be configured in various
ways depending on the input signal and the required level of
performance. A signal voltage with a maximum span of V
RT
-
V
RB
can be AC coupled to the HI5714 through the V
IN2
BNC
and applied to the ADC by installing jumper JP2. P4 would
be adjusted to center the signal in the range of the HI5714.
This may or may not be adequate depending on the type of
input signal.
An HA5020 buffer (as shown in Figure 5) is also provided
that can be used to drive the part by inserting JP1. The gain
of the circuit can be calculated from:
R
9
R
1
R
9
-
V
OUT
= –
------
V
IN
+
1
+ ------
--------------------
V
OFFSET
-
-
R
7
R
1
+
R
2
R
7
Figure 6 shows the timing for the evaluation board. The data
corresponding to a particular sample will be available at the
output of the HI5714 after the required data latency (1 cycle)
plus an output delay. Table 2 lists the values that can be
expected for the various timing delays. Refer to the
datasheet for additional timing information.
CLK1
INPUT
t
PD1
HI5714
CLOCK
INPUT
HI5714
DATA0-7
OUTPUT
The combination of the buffer and the external reference will
give the best performance for the HI5714 and allow the most
flexibility when dealing with various types of input signals. If
an application is extremely cost sensitive then the internal
bias generators along with the AC coupled version of the
input circuit can be used.
R
9
R
7
V
IN
-
+
0.1µF
V
OFFSET
R
2
R
1
R
2
V
IN
t
OD
DATA
t
PD2
DATA
CLK OUT
(74ACT04)
t
PD3
DOUT0-7
(74ACT541)
DATA
DATA
FIGURE 5. MODIFIED BUFFER
FIGURE 6. INPUT-TO-OUTPUT TIMING
3
Application Note 9517
DAC Setup
The HI5721 is used as a reconstruct DAC to allow the user
to easily view the performance of the HI5714. The HI5721 is
a TTL, 10-bit, 125MHz DAC.
The internal reference in the HI5721 is a -1.25V (typical)
bandgap voltage reference with a 100µV/
o
C temperature
drift. The internal reference should be buffered by the Con-
trol Amplifier to provide adequate drive for the segmented
current cells and the R2/R resistor ladder. Reference Out
(REF OUT) should be connected to the Control Amplifier
Input (CTRL AMP IN). The Control Amplifier Output (CTRL
AMP OUT) should be used to drive the Reference Input
(REF IN) and a 0.1µF capacitor to analog V-(-AV
EE
). This
improves settling time by decoupling switching noise from
the analog output of the HI5721.
The Full Scale Output Current is controlled by the CTRL
AMP IN pin and the set resistor (R
SET
). The ratio is:
I
OUT
(Full Scale) = (CTRL AMP IN/R
SET
) x 32
The outputs I
OUT
and I
OUT
are complementary current out-
puts. Current is steered to either I
OUT
or I
OUT
in proportion to
the digital input code. The sum of the two currents is always
equal to the full scale current minus one LSB. The current
output can be converted to a voltage by using a resistor load.
Both current outputs should have the same load (50Ω typi-
cally). The output voltage is:
V
OUT
= I
OUT
x R
OUT
The compliance range of the outputs is from -1.5V to +3.0V.
m
×
k
T
= -------------
-
F
S
Where:
F
S
= sampling frequency of the ADC.
FSR = full scale range of the ADC.
k = desired test resolution (number of conversions per LSB).
m = desired number of steps (LSBs) per ramp period.
n = number of bits of the ADC.
For example, if k = 10, n = 8, m = 16, F
S
= 20 MSPS, and
FSR = 1V then the input ramp would have a V
P-P
of 62.5mV
and a period (T) of 8µs. To view the reconstructed output,
connect the X axis of an oscilloscope to the ramp input and
the Y axis would be connected to the reconstruction DAC
output. Another oscilloscope could be used to probe the bits
to verify the codes that are being tested. The analog input
should be low pass filtered to remove as much noise as pos-
sible. Notice that the input ramp is only covering m steps out
a possible 2
n
possible for the ADC. Therefore, the generator
used for this test will have to be able to offset the input
through the range of the converter so all the codes for the
ADC can be inspected.
Figure 8 shows what an ideal reconstructed output would
look like with and without various errors. For an ideal ADC
and an ideal ramp input, the digital output code will change
state by 1 LSB every kth conversion for an 1 LSB change on
the input. ADC errors will make the codes change before or
after the kth conversion and will translate to a larger or
smaller step width. The actual step width size would be com-
pared with the ideal LSB size to determine errors. Since this
is a visual comparison it will tend not to be very precise.
HI5714 Characterization
Various tests can be used to characterize the performance of
the HI5714. The integral nonlinearity (INL) and differential
nonlinearity (DNL) specs are considered a measure of the
low frequency characteristics of the ADC. These parameters
are evaluated at the factory using a histogram approach with
a low frequency ramp input.
A three bit reconstruction DAC, as shown in Figure 7, can be
constructed to do a rough evaluation of HI5714 for DNL,
missing codes, and transition noise.
1K
DOUT2
2K
DOUT1
4K
DOUT0
OSCILLOSCOPE
RAMP INPUT
111
110
101
100
011
B
FIGURE 7. THREE BIT RECONSTRUCTION DAC
The input frequency is set so that the input will changes by
1 LSB for every k conversions of the ADC. The p-to-p volt-
age of the staircase is then determined by the number of
LSB steps within one period of the input ramp. The following
equations can be used:
m
×
FSR
V
P
–
P
= -----------------------
-
2
n
010
001
000
1 LSB
MAJOR TRANSITION
NOISE
B - MISSING
CODE
FIGURE 8. THREE BIT DAC WAVEFORMS
4
Application Note 9517
Further dynamic testing is used to evaluate the HI5714
performance as the input starts to approach Nyquist (F
S
/2).
Among these tests are Signal-to-Noise Ratio (SNR), Signal-
to-Noise And Distortion (SINAD), and Total Harmonic
Distortion (THD).
Coherent testing is recommended in order to avoid the
inaccuracies due to windowing. Coherent sampling is
governed by the following relationship: F
T
/F
S
= M/N. Where
F
T
is the frequency of the input tone, F
S
is the sampling
frequency, N is the number of samples, and M is the number
of cycles over which the samples are taken. By making M an
integer and prime (1, 3, 5. . .) the samples are assured of
being non-repetitive.
Figure 9 shows the test system used to do dynamic testing
on the HI5714. The clock (CLK) and analog input (AIN) sig-
nal sources are derived from low phase noise HP8662A
generators that are phase locked to each other to ensure
coherence. The output of the generator that drives the ana-
log input to the evaluation board is first passed through a
bandpass filter to improve the spectral purity of the signal.
The ADC data is captured by a logic analyzer and then
transferred over the GPIB bus to the PC. The PC has all the
software to perform the Fast Fourier (FFT) and do the
required data analysis.
A 10-bit accurate DAC is used to do the bandwidth testing.
The input sine wave has a peak-to-peak amplitude equal to
the reference voltage. The CLK and analog input frequen-
cies are set up so a 1kHz beat frequency is generated on the
output of the DAC. Full power bandwidth is the frequency at
which the amplitude of the digitally reconstructed output is
3dB down from the low frequency value.
Refer to the HI5714 datasheet for a complete list of test
definitions and the results that can be expected using the
evaluation board.
HP8662A
LOCK
HP8662A
HP8662A
HP PULSE
GENERATOR
BAND-PASS
FILTER
HP PULSE
GENERATOR
VIDEO
GENERATOR
AIN
CLK
HI5714
DIG OUT
8
CLK
AIN
HI5714
DIG OUT
8
HI5714 EVALUATION BOARD
HI5714 EVALUATION BOARD
DAC
DAC
DAS LOGIC
ANALYZER
GPIB
OSCILLOSCOPE
PC
OSCILLOSCOPE
VM700
FIGURE 9. COHERENT TEST SYSTEM
FIGURE 10. VIDEO TEST SYSTEM
5
FPGA/CPLD
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