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VT-704-HFE-1560-26M0000000_SNPBDIP

产品描述Clipped Sine Output Oscillator, 26MHz Nom, SMD, 4 PIN
产品类别无源元件    振荡器   
文件大小845KB,共8页
制造商Microsemi
官网地址https://www.microsemi.com
下载文档 详细参数 全文预览

VT-704-HFE-1560-26M0000000_SNPBDIP概述

Clipped Sine Output Oscillator, 26MHz Nom, SMD, 4 PIN

VT-704-HFE-1560-26M0000000_SNPBDIP规格参数

参数名称属性值
是否Rohs认证不符合
Objectid4005837012
包装说明SMD, 4 PIN
Reach Compliance Codecompliant
老化1 PPM/FIRST YEAR
频率调整-机械NO
频率稳定性1.5%
JESD-609代码e0
安装特点SURFACE MOUNT
端子数量4
标称工作频率26 MHz
最高工作温度85 °C
最低工作温度-40 °C
振荡器类型CLIPPED SINE
输出阻抗10000 Ω
输出电平0.8 V
封装主体材料CERAMIC
封装等效代码DILCC4,.2,200
物理尺寸7.0mm x 5.0mm x 1.9mm
最大压摆率3.5 mA
最大供电电压2.625 V
最小供电电压2.375 V
标称供电电压2.5 V
表面贴装YES
端子面层Tin/Lead (Sn/Pb)

VT-704-HFE-1560-26M0000000_SNPBDIP文档预览

VT-704
Temperature Compensated Crystal Oscillator
VT-704
Description
Vectron’s VT-704 Temperature Compensated Crystal Oscillator (TCXO) is a quartz stabilized, Clipped sine wave or CMOS output,
analog temperature compensated oscillator, operating off a 2.5V to 3.3 volt supply in a hermetically sealed 7.0 x 5.0 mm ceramic
package.
Features
Clipped Sine Wave or CMOS Output
5.000 - 52.000MHz Output Frequency
±0.5ppm Temperature Stability
Optional Frequency Tuning
Fundamental Crystal Design
Gold over nickel contact pads
Hermetically Sealed Ceramic SMD package
Applications
Femto Cells
Base Stations
IP Networking
Global Positioning Systems
Point to Point Radio
Manpack Radio
Test and Measurement
• Product is compliant to RoHS directive
and fully compatible with lead free assembly
Block Diagram
V
DD
Crystal
Output
Analog
Temperature
Comp.
V
CONTROL
(Optional)
Gnd
Page1
Specifications
Table 1. Electrical Performance, Clipped Sine Wave Option
Parameter
Output Frequency
1
,
Ordering Option
Supply Voltage
3
,
Ordering Option
Supply Current
Operating Temperature,
Ordering Option
Stability Over T
OP4
,
Ordering Option
Frequency Tolerance
5
Power Supply Stability, ±5%
Load Stability, ±10%
Aging / 1st year
Tuning Range
6
Tuning Slope
Control Voltage to reach Pull Range
Control Voltage Impedance
Output Level High
Output Load
Start Up Time
Phase Noise, 10.00MHz
7
10Hz
100Hz
1kHz
10kHz
100kHz
V
O
p-p
C
L
t
SU
Phase Noise
7
N
Symbol
f
O
V
DD
I
DD
T
OP
F
STAB
F
TOL
F
PWR
F
LOAD
F
AGE
Min.
5
Typ
+2.5, +2.8, +3.0, +3.3
Max
52
3.5
Units
MHz
V
mA
°C
ppm
ppm
ppm
ppm
ppm
ppm
0/55, -10/70, -20/70, -30/80, -30/85, -40/85
±0.5, ±1.0, ±1.5 , ±2.0, ±2.5, ±3.0, ±4.0, ±5.0
±2.0
±0.1
±0.2
±1.0
±5.0, ±8.0, ±10.0, ±12.0
Positive
0.5
100
1.5
2.5
Frequency Stability
Frequency Tuning (EFC),
Ordering Option
PR
V
C
V
Kohm
V
RF Output (Clipped Sine Wave),
Ordering Option
0.8
10k || 10pF
2
ms
dBc/Hz
-96
-122
-140
-148
-153
1. Refer to Table 8 for Standard Frequencies. Other Frequencies are available on request. Check with factory.
2. Output DC-cut capacitor is optional.
3. The VT-704 power supply pin (Pin4) should be filtered using a by-pass capacitor of 0.1uF for optimal performance.
4. Referenced to the midpoint between minimum and maximum frequency value over Operating Temperature Range.
5. Frequency measured at 25 °C, 1 hour after 2 IR reflows.
6. Referenced to Mid Control Voltage
7. Measured at ambient temperature using Agilent E5052B Signal Source Analyzer.
Page2
Table 2. Electrical Performance, CMOS Option
Parameter
Output Frequency
1
,
Ordering Option
Supply Voltage
3
,
Ordering Option
Supply Current
Operating Temperature,
Ordering Option
Stability Over T
OP4
,
Ordering Option
Frequency Tolerance
5
Power Supply Stability, ±5%
Load Stability, ±10%
Aging / 1st year
Tuning Range
6
Tuning Slope
Control Voltage to reach Pull Range
Control Voltage Impedance
Output Level High
Output Level Low
Output Load
Duty Cycle
Start Up Time
Rise & Fall Times
Phase Noise
7
Phase Noise, 10.00MHz
7
10Hz
100Hz
1kHz
10kHz
100kHz
N
Symbol
f
O
V
DD
I
DD
T
OP
F
STAB
F
TOL
F
PWR
F
LOAD
F
AGE
Min.
5
Typ
+2.5, +2.8, +3.0, +3.3
Max
52
6.0
Units
MHz
V
mA
°C
ppm
ppm
ppm
ppm
ppm
ppm
0/55, -10/70, -20/70, -30/80, -30/85, -40/85
±0.5, ±1.0, ±1.5 , ±2.0, ±2.5, ±3.0, ±4.0, ±5.0
±2.0
±0.1
±0.2
±1.0
±5.0, ±8.0, ±10.0, ±12.0
Positive
0.5
100
1.5
2.5
Frequency Stability
Frequency Tuning (EFC),
Ordering Option
PR
V
C
V
Kohm
V
RF Output (CMOS),
Ordering Option
V
OH
V
OL
C
L
45
t
SU
0.9*V
DD
0.1*V
DD
15
55
2
4
pF
%
ms
ns
dBc/Hz
-98
-129
-145
-153
-156
1. Refer to Table 8 for Standard Frequencies. Other Frequencies are available on request. Check with factory.
2. Output DC-cut capacitor is optional.
3. The VT-704 power supply pin (Pin4) should be filtered using a by-pass capacitor of 0.1uF for optimal performance.
4. Referenced to the midpoint between minimum and maximum frequency value over Operating Temperature Range.
5. Frequency measured at 25 °C, 1 hour after 2 IR reflows.
6. Referenced to Mid Control Voltage.
7. Measured at ambient temperature using Agilent E5052B Signal Source Analyzer
Page3
Phase Noise Performance for 10MHz Clipped Sine Wave
Phase Noise Performance for 10MHz CMOS
Page4
Package Outline Drawing & Pad Layout
XXMXXX
YYWW T
Dimensions in mm
Table 3. Pinout
Pin #
1
Marking Information
XXMXX - Frequency (Example: 10M000)
YY - Year of Manufacture
WW - Week of the Year
T - Manufacturing Location
- Pin 1 Indicator
2
3
4
Symbol
Vc or NC
GND
OUT
V
DD
Function
TCXO Control Voltage or No Connect
Ground
RF Output
Supply Voltage
Note:
0.1uF capacitor is a by-pass power supply filter capacitor
placed between Pin4 (Vdd) and Ground for optimal
performance.
VCXO Function
S
VCXO Feature:
The VT-704 is supplied with a VCXO function for applications were it will be used in a PLL, or the output frequency needs
fine tune or calibration adjustments. This is a high impedance input, 100kOhm, and can be driven with an op-amp or terminated with
adjustable resistors etc.
Pin1 should not be left floating on the VCXO optional device.
Maximum Ratings
S
Absolute Maximum Ratings and Handling Precautions
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied or any other
excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended
periods may adversely affect device reliability.
Although ESD protection circuitry has been designed into the VT-704, proper precautions should be taken when handling and mounting,
VI employs a Human Body Model and Charged Device Model for ESD susceptibility testing and design evaluation.
ESD thresholds are dependent on the circuit parameters used to define the model. Although no industry standard has been adopted for
the CDM a standard resistance of 1.5kOhms and capacitance of 100pF is widely used and therefor can be used for comparison purposes.
Table 4. Maximum Ratings
Parameter
Storage Temperature
Supply Voltage
Control Voltage
Enable/Disable Voltage
ESD, Human Body Model
ESD, Charged Device Model
Symbol
T
STORE
V
DD
V
C
E/D
Rating
-55/125
-0.6/6
-0.6/V
DD
+0.6
-0.6/V
DD
+0.6
1500
1000
Unit
ºC
V
V
V
V
V
Page5
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