Revision 0
SmartFusion2 System-on-Chip FPGAs
Microsemi’s SmartFusion
®
2 SoC FPGAs integrate fourth generation flash-based FPGA fabric, an ARM
®
Cortex™-M3 processor,
and high performance communications interfaces on a single chip. The SmartFusion2 family is the industry’s lowest power, most
reliable and highest security programmable logic solution. This next generation SmartFusion2 architecture offers up to 3.6X gate
count implemented with 4-input look-up table (LUT) fabric with carry chains, giving 2X performance, and includes multiple embedded
memory options and math blocks for digital signal processing (DSP). The 166 MHz ARM Cortex-M3 processor is enhanced with an
embedded trace macrocell (ETM), memory protection unit (MPU), 8 Kbyte instruction cache, and additional peripherals including
controller area network (CAN), Gigabit Ethernet, and high speed universal serial bus (USB). High speed serial interfaces include
peripheral component interconnect express (PCIe), 10 Gbps attachment unit interface (XAUI) / XGMII extended sublayer (XGXS) +
native serialization/deserialization (SERDES) communication, while double data rate 2 (DDR2)/DDR3 memory controllers provide
high speed memory interfaces.
SmartFusion2 Family
Reliability
•
•
Single Event Upset (SEU) Immune
–
Zero FIT FPGA Configuration Cells
•
Single Error Correct Double Error Detect (SECDED)
Protection on the Following:
–
–
–
–
–
–
•
Ethernet Buffers
CAN Message Buffers
Cortex-M3
(eSRAMs)
USB Buffers
PCIe Buffer
DDR Memory Controllers with Optional SECDED
Modes
•
•
Embedded
Scratch
Pad
Memory
–
–
–
–
–
–
–
Enhanced Anti-Tamper Features
Zeroization
Non-Deterministic Random Bit Generator (NRBG)
User Cryptographic Services (AES-256, SHA-256,
Elliptical Curve Cryptographic (ECC) Engine)
User Physically Unclonable Function (PUF) Key
Enrollment and Regeneration
CRI Pass-Through DPA Patent Portfolio License
Hardware Firewalls Protecting
Subsystem (MSS) Memories
Microcontroller
Data Security Features (available on premium devices)
Low Power
Low Static and Dynamic Power
–
–
–
•
•
•
Flash*Freeze Mode for Fabric
< 1 mW in Flash*Freeze Mode
10 mW in Standby Mode
For the M2S050 Device:
Buffers Implemented with SEU Resistant Latches on the
Following:
–
–
–
–
DDR Bridges (MSS, MDDR, FDDR)
Instruction Cache
MMUART FIFOs
SPI FIFOs
Based on 65 nm Nonvolatile Flash Process
Efficient 4-Input LUTs with Carry Chains for High
Performance and Low Power
Up to 236 Blocks of Dual-Port 18 Kbit SRAM (Large
SRAM) with 400 MHz Synchronous Performance (x18,
x9, x4, x2, x1)
Up to 240 Blocks of Three-Port 1 Kbit SRAM with 2
Read Ports and 1 Write Port (micro SRAM)
High Performance DSP Signal Processing
–
Up to 240 Fast Math Blocks with 18 x 18 Signed
Multiplication, 17 x 17 Unsigned Multiplication and
44-Bit Accumulator
•
•
NVM Integrity Check at Power-Up and On-Demand
No External Configuration Memory Required—Instant-
On, Retains Configuration When Powered Off
Design Security Features (available on all devices)
–
Intellectual Property (IP) Protection via Unique
Security Features and Use Models New to the PLD
Industry
Encrypted User Key and Bitstream Loading,
Enabling Programming in Less-Trusted Locations
Supply-Chain Assurance Device Certificate
High-Performance FPGA
Security
•
•
•
–
–
October 2012
© 2012 Microsemi Corporation
I
SmartFusion2 System-on-Chip FPGAs
Microcontroller Subsystem (MSS)
•
Hard 166 MHz 32-Bit ARM Cortex-M3 Processor
–
–
–
–
–
–
•
•
•
•
•
•
•
•
•
•
•
1.25 DMIPS/MHz
8 Kbyte Instruction Cache
Embedded Trace Macrocell (ETM)
Memory Protection Unit (MPU)
Single Cycle Multiplication, Hardware Divide
JTAG Debug (4 wires), Serial Wire Debug (SWD, 2
wires), and Serial Wire Viewer (SWV) Interfaces
High Speed Serial Interfaces
•
Up to 16 SERDES Lanes, Each Supporting:
–
–
XGXS/XAUI Extension (to implement a 10 Gbps
(XGMII) Ethernet PHY interface)
Native SERDES Interface Facilitates Implementation
of Serial RapidIO in Fabric or an SGMII Interface to
the Ethernet MAC in MSS
PCI Express (PCIe) Endpoint Controller
x1, x2, x4 Lane PCI Express Core with 16-bit
PIPE Interface (Gen1/Gen2)
256 Bytes Maximum Payload Size
64-/32-Bit AXI/AHB Master and Slave Interfaces
to the Application Layer
–
64 KB Embedded SRAM (eSRAM)
Up to 512 KB Embedded Nonvolatile Memory (eNVM)
Triple Speed Ethernet (TSE) 10/100/1000 Mbps MAC
USB 2.0 High Speed On-The-Go (OTG) Controller with
ULPI Interface
CAN Controller, 2.0B Compliant, Conforms
ISO11898-1, 32 Transmit and 32 Receive Buffers
to
•
High Speed Memory Interfaces
Up to 2 High Speed DDRx Memory Controllers
–
–
–
–
–
–
–
•
•
•
MSS DDR (MDDR) and Fabric DDR (FDDR)
Controllers
Supports LPDDR/DDR2/DDR3
Maximum 333 MHz Clock Rate
SECDED Enable/Disable Feature
Supports Various DRAM Bus Width Modes, x16,
x18, x32, x36
Supports Command Reordering to Optimize Memory
Efficiency
Supports Data Reordering, Returning Critical Word
First for Each Command
Two Each: SPI, I
2
C, Multi-Mode UARTs (MMUART)
Peripherals
Hardware Based Watchdog Timer
1 General Purpose 64-Bit (or two 32-bit) Timer(s)
Real-Time Calendar/Counter (RTC)
DDR Bridge (4 Port Data R/W Buffering Bridge to DDR
Memory) with 64-Bit AXI Interface
Non-Blocking, Multi-Layer AHB Bus Matrix Allowing
Multi-Master Scheme Supporting 10 Masters and 7
Slaves
Two AHB/APB Interfaces to FPGA Fabric (master/slave
capable)
Two DMA Controllers to Offload Data Transactions from
the Cortex-M3 Processor
–
–
8-Channel Peripheral DMA (PDMA) for Data
Transfer Between MSS Peripherals and Memory
High Performance DMA (HPDMA) for Data Transfer
Between eSRAM and DDR Memories
•
•
SDRAM Support
1.2 V Core Voltage
Multi-Standard User I/Os (MSIO/MSIOD)
–
–
–
–
–
–
–
LVTTL/LVCMOS 3.3 V
LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V
DDR (SSTL2_1, SSTL2_2)
DDR2 (SSTL18_1, SSTL18_2)
LVDS, MLVDS,
Standards
PCI
LVPECL (receiver only)
DDR, DDR2, DDR3, LPDDR, SSTL2, SSTL18,
HSTL
LVCMOS 1.2 V, 1.5 V, 1.8 V, 2.5 V
Mini-LVDS,
RSDS
Differential
Operating Voltage and I/Os
Clocking Resources
•
Clock Sources
–
–
–
•
Up to Two High Precision 32 KHz to 20 MHz Main
Crystal Oscillator
1 MHz Embedded RC Oscillator
50 MHz Embedded RC Oscillator
•
DDR I/Os (DDRIO)
–
–
Up to 8 Clock Conditioning Circuits (CCCs) with Up to 8
Integrated Analog PLLs
–
–
Output Clock with 8 Output Phases and 45° Phase
Difference (Multiply/Divide, and Delay Capabilities)
Frequency: Input 1 to 200 MHz, Output 20 to 400
MHz
II
R ev i si o n 0
SmartFusion2 System-on-Chip FPGAs
SmartFusion2 SoC FPGA Block Diagram
JTAG I/O
SPI I/O
Multi-Standard User I/O (MISO)
DDR User I/O
System Controller
AES256
SHA256
SRAM-PUF
SPI x 2
MMUART x 2
I2C x 2
Timer x 2
Microcontroller
Subsystem (MSS)
APB
PDMA
ARM
®
Cortex
™
-M3
MPU
ETM
D
I
S
Instruction
Cache
CAN
WDT
RTC
AHB Bus Matrix (ABM)
FIIC
HS USB
OTG ULPI
ECC
NRBG
SYSREG
eNVM
DDR
Bridge
Flash*Freeze
In-Application
Programming
MSS
DDR Controller
+ PHY
Multi-Standard User I/O (MISO)
eSRAM
Multi-Standard User I/O (MISO)
andard
COMM_BLK
FIC_0
FIC_1
TSE MAC
HPDMA
Interupts
AHB
AHB
AHB
SMC_FIC Config
AXI/AHB
FPGA Fabric
Micro SRAM
(64x18)
Large SRAM
(1024x18)
Math Block
MACC (18x18)
Micro SRAM
(64x18)
Large SRAM
(1024x18)
Math Block
MACC (18x18)
Config
AXI/AHB/XGXS
Config
AXI/AHB/XGXS
Config
AXI/AHB
Standard Cell /
SEU Immune
Flash Based /
SEU Immune
Serial Controller 0
(PCIe, XAUI/XGXS)
+ Native SERDES
OSCs
Serial Controller 1
(PCIe, XAUI/XGXS)
+ Native SERDES
PLLs
Fabric DDR
Controller + PHY
Serial 0 I/O
Serial 1 I/O
DDR User I/O
Acronyms
AES
AHB
APB
AXI
COMM_BLK
DDR
DPA
ECC
EDAC
ETM
FDDR
FIC
FIIC
HS USB OTG
IAP
MACC
Advanced Encryption Standard
Advanced High-Performance Bus
Advanced Peripheral Bus
Advanced eXtensible Interface
Communication Block
Double Data Rate
Differential Power Analysis
Elliptical Curve Cryptography
Error Detection And Correction
Embedded Trace Macrocell
DDR2/3 controller in FPGA fabric
Fabric Interface Controller
Fabric Interface Interrupt Controller
High Speed USB 2.0 On-The-Go
In-Application Programming
Multiply-Accumulate
MDDR
MMUART
MPU
MSS
SECDED
SEU
SHA
SMC_FIC
TSE
ULPI
UTMI
WDT
XAUI
XGMII
XGXS
DDR2/3 Controller in MSS
Multi-Mode UART
Memory Protection Unit
Microcontroller Subsystem
Single Error Correct Double Error Detect
Single Event Upset
Secure Hashing Algorithm
Soft Memory Controller
Triple Speed Ethernet (10/100/1000 Mbps)
UTMI + Low Pin Interface
USB 2.0 Transceiver Macrocell Interface
Watchdog Timer
10 Gbps Attachment Unit Interface
10 Gigabit Media Independent Interface
XGMII Extended Sublayer
R e visi on 0
III
SmartFusion2 System-on-Chip FPGAs
Table 1 • SmartFusion2 SoC FPGA Product Family
Features
M2S005
4,956
10
11
191K
11
2
Yes
128K
64K
80K
1
1
1
2
2
2
2
1x18
0
0
123
28
66
217
0
217
M2S010
9,744
21
22
400K
22
2
Yes
256K
64K
80K
1
1
1
2
2
2
2
1x18
4
1
123
40
70
233
16
249
M2S025
23,988
31
34
592K
34
4
Yes
256K
64K
80K
1
1
1
2
2
2
2
1x18
4
1
159
40
90
289
16
305
M2S050
48,672
69
72
1,314K
72
6
Yes
256K
64K
80K
1
1
1
2
2
2
2
2x36
8
2
139
62
176
377
32
409
M2S080
82,232
160
160
3,040K
160
8
Yes
512K
64K
80K
1
1
1
2
2
2
2
2x36
8
2
292
106
176
574
64
638
M2S120
120,348
236
240
4,500K
240
8
Yes
512K
64K
80K
1
1
1
2
2
2
2
2x36
16
4
292
106
176
574
64
638
Logic Modules (4-Input LUT)
LSRAM 18K Blocks
FPGA
MSS
Memory,
Serial I/F
User I/O
uSRAM 1K Blocks
Total RAM (Bits)
Math Blocks
PLLs and CCCs
Cortex-M3 Processor + Instruction Cache
eNVM (Bytes)
eSRAM (Bytes)
eSRAM (Bytes non-SECDED)
CAN 2.0 A and B
Triple speed Ethernet 10/100/1000
USB 2.0 High Speed On-The-Go
Multi-Mode UART
SPI
I2C
Timer
DDR Controllers
SERDES Channels
PCIe Endpoint × 4
3.3 V Multi-Standard User I/Os (MSIOs)
MSIOD I/Os
DDRIO I/Os
Total User I/Os
SERDES I/Os
Total User I/Os + SERDES I/Os
I/Os Per Package
Table 2 • I/Os per Package and Package Options
Package Options
Pin Count
Ball Pitch (mm)
Length × Width (mm\mm)
M2S005
M2S010
M2S025
M2S050
M2S080
M2S120
I/Os
160
160
160
160
–
–
VF400
400
0.8
17 × 17
XCVRs
–
4
4
4
–
–
I/Os
217
233
267
267
–
–
FG484
484
1.0
23 × 23
XCVRs
–
4
4
4
–
–
I/Os
–
–
–
377
–
–
FG896
896
1.0
31 × 31
XCVRs
–
–
–
8
–
–
–
–
–
–
574
574
I/Os
FC1152
1,152
1.0
35 × 35
XCVRs
–
–
–
–
8
16
Note:
User I/Os do not include the SERDES and JTAG pins.
IV
R ev i si o n 0
SmartFusion2 System-on-Chip FPGAs
SmartFusion2 Ordering Information
.
M2S050
T
S
_
1
FG
G
144
Y
I
Application (Temperature Range)
Blank = Commercial (0°C to +85°C Ambient Temperature)
I = Industrial (
–
40°C to +100°C Ambient Temperature)
ES = Engineering Sample (Room Temperature Only)
Security Feature
Y = Device Includes License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS-Compliant
Package Type
FG = Fine Pitch Ball Grid Array (1.0 mm pitch)
VF = Very Fine Pitch Ball Grid Array (0.8 mm pitch)
Speed Grade
Blank = TBD
1 = TBD
Security
Blank = Design Security
S = Data and Design Security
Transceiver
T = With Transceiver
Blank = No Transceiver
Part Number (Digits Indicate Thousands of LUTs)
M2S005
M2S010
M2S025
M2S050
M2S080
M2S120
R e visi on 0
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