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www.fairchildsemi.com
TMC2246A
Image Filter
11 x 10 bit, 60 MHz
Features
60 MHz computation rate
60 MHz data and coefficient input
Four 11 x 10-bit multipliers
Individual data and coefficient inputs
25-Bit accumulator
Fractional and integer two’s complement data formats
Input and output data latches with user-configurable
enables
• Selectable 16-bit rounded output
• Internal 1/2 LSB rounding
• Available in 120-pin CPGA, PPGA, MPGA, or MQFP
•
•
•
•
•
•
•
Applications
•
•
•
•
•
•
Fast pixel interpolation
Fast image manipulation
Image mixing and keying
High-performance FIR filters
Adaptive digital filters
One- and two-dimensional image processing
Description
The TMC2246A is a video-speed convolutional array com-
posed of four 11 x 10 bit registered multipliers followed by a
summer and an accumulator. All eight multiplier inputs are
accessible to the user and may be updated every clock cycle
with integer or fractional two’s complement data. A pipe-
lined architecture, fully registered input and output ports,
and asynchronous three-state output enable control simplify
the design of complex systems.
The data or coefficient inputs to the multipliers may be held
over multiple clock cycles, providing storage for mixing and
filtering coefficients. The 25-bit internal accumulator path
allows two bits of cumulative word growth and may be inter-
nally rounded to 16 bits. Output data are updated every clock
cycle, or may be held under user control. All data inputs, out-
puts, and controls are TTL compatible and (except for the
three-state output enable) are registered on the rising edge of
CLK.
The TMC2246A is uniquely suited to performing pixel inter-
polation in image manipulation and filtering applications. As
a companion to the Fairchild Semiconductor TMC2301 and
TMC2302 Image Manipulation Sequencers, the TMC2246A
can execute a bilinear interpolation of an image (4-pixel ker-
nels) at real-time video rates. Larger kernels or other, more
complex, functions can be realized with no loss in performance
by utilizing multiple devices.
With unrestricted access to all data and coefficient input
ports, the TMC2246A offers considerable flexibility in appli-
cations performing digital filtering, adaptive FIR filters, mix-
ers, and other similar systems requiring high-speed
processing.
Fabricated in a submicron CMOS process, the TMC2246A
operates at a guaranteed clock rate of 60 MHz over the full
temperature and supply voltage ranges. It is pin- and func-
tion-compatible with Fairchild’s TMC2246, while providing
higher speed operation and lower power dissipation. It is
available in a 120 pin Plastic Pin Grid Array (PPGA), 120
pin Ceramic Pin Grid Array (CPGA), 120 lead MQFP to
PPGA (MPGA), and a 120 lead Metric Quad FlatPack
(MQFP).
REV. 1.0.3 9/11/00
Logic Symbol
TMC2246A
Image Filter
D1
9-0
C1
10-0
D2
9-0
C2
10-0
D3
9-0
C3
10-0
D4
9-0
C4
10-0
ENB1-4
ENSEL
ACC
FSEL
S
15-0
OCEN
OEN
CLK
PRODUCT SPECIFICATION
TMC2246A
Block Diagram
D19-0 C110-0 ENB1 D29-0 C210-0 ENB2 D39-0 C310-0 ENB3 D4 9-0 C410-0 ENB4
ENSEL
ACC
FSEL
*
2 -10
25
OCEN
LSB
MSB
CLK
OEN
*Automatic rounding function
S15-0
Functional Description
The TMC2246A Image Filter is a flexible multiplier-summer
array which computes the accumulated sum of four 11x10
bit products, allowing word growth up to 25 bits.
The inputs are user-configurable, allowing latching of either
the 10- or 11-bit input data. The data format is user-selectable
between integer or fractional two’s complement arithmetic.
Total latency from input registers to output data port is 5
clocks.
The output data path is 16 bits wide, providing the lower 16
bits of the accumulator when in integer format or the upper
16 bits of the 25-bit accumulator path when fractional two’s
complement notation is selected. One-time rounding to 16
bits is performed automatically when accumulating frac-
tional data, but is disabled when operating in integer format
to maintain the integrity of the least-significant bits.
2
REV. 1.0.3 9/11/00
TMC2246A
PRODUCT SPECIFICATION
Pin Assignments
120 Pin Plastic Pin Grid Array, H5 Package, 120 Pin Ceramic Pin Grid Array, G1 Package, and
120 Pin Metric Quad FlatPack to 120 Pin Plastic Pin Array, H6 Package
1
A
B
C
D
E
F
G
H
J
K
L
M
N
Top View
Cavity Up
KEY
2
3
4
5
6
7
8
9
10 11 12 13
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
C1
C2
C3
C4
Name
ENSEL
ENB2
ENB3
D47
D45
D42
D41
C410
C48
C46
C43
C40
C32
ACC
FSEL
ENB4
D49
D46
D43
D40
C49
C47
C44
C42
C30
C35
S15
OEN
CLK
ENB1
Pin
C5
C6
C7
C8
C9
C10
C11
C12
C13
D1
D2
D3
D11
D12
D13
E1
E2
E3
E11
E12
E13
F1
F2
F3
F11
F12
F13
G1
G2
G3
Name
D48
D44
GND
VDD
C45
C41
C31
C33
C36
S13
S14
OCEN
C34
C37
C39
S11
S12
GND
C38
C310
D30
S9
S10
VDD
D31
D32
D33
S7
S8
GND
Pin
G11
G12
G13
H1
H2
H3
H11
H12
H13
J1
J2
J3
J11
J12
J13
K1
K2
K3
K11
K12
K13
L1
L2
L3
L4
L5
L6
L7
L8
L9
Name
D35
D36
D34
S6
S5
VDD
GND
D38
D37
S4
S3
GND
D27
D29
D39
S2
S1
D18
D23
D26
D28
S0
D17
D15
D12
C19
GND
VDD
C20
C24
Pin
L10
L11
L12
L13
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
Name
C28
D20
D24
D25
D19
D14
D11
C110
C17
C15
C13
C10
C22
C25
C29
D21
D22
D16
D13
D10
C18
C16
C14
C12
C11
C21
C23
C26
C27
C210
REV. 1.0.3 9/11/00
3
PRODUCT SPECIFICATION
TMC2246A
Pin Assignments
120 Lead Metric Quad Flat Pack (KE) Package
120
1
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
CLK
FSEL
ACC
OCEN
OEN
S
15
S
14
GND
S
13
S
12
S
11
V
DD
S
10
S
9
S
8
GND
S
7
S
6
S
5
V
DD
S
4
S
3
S
2
GND
Pin
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Name
S
1
S
0
D1
9
D1
8
D1
7
D1
6
D1
5
D1
4
D1
3
D1
2
D1
1
D1
0
C1
10
C1
9
C1
8
C1
7
C1
6
GND
C1
5
C1
4
C1
3
V
DD
C1
2
C1
1
Pin
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Name
C1
0
C2
0
C2
1
C2
2
C2
3
C2
4
C2
5
C2
6
C2
7
C2
8
C2
9
C2
10
D2
0
D2
1
D2
2
D2
3
D2
4
D2
5
D2
6
D2
7
D2
8
D2
9
D3
9
GND
Pin
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Name
D3
8
D3
7
D3
6
D3
5
D3
4
D3
3
D3
2
D3
1
D3
0
C3
10
C3
9
C3
8
C3
7
C3
6
C3
5
C3
4
C3
3
C3
2
C3
1
C3
0
C4
0
C4
1
C4
2
C4
3
Pin
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Name
C4
4
C4
5
C4
6
C4
7
C4
8
V
DD
C4
9
C4
10
D4
0
GND
D4
1
D4
2
D4
3
D4
4
D4
5
D4
6
D4
7
D4
8
D4
9
ENB3
ENB2
ENB1
ENB4
ENSEL
4
REV. 1.0.3 9/11/00
FPGA/CPLD
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