74HCU04-Q100
Hex inverter
Rev. 1 — 31 January 2013
Product data sheet
1. General description
The 74HCU04-Q100 is a hex unbuffered inverter. Inputs include clamp diodes that enable
the use of current limiting resistors to interface inputs to voltages in excess of V
CC
.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Complies with JEDEC standard JESD7A
Balanced propagation delays
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Ordering information
Table 1.
Ordering information
Package
Temperature
range
74HCU04D-Q100
Name
Description
plastic small outline package; 14 leads; body width
3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
40 C
to +125
C
SO14
74HCU04PW-Q100
40 C
to +125
C
TSSOP14
74HCU04BQ-Q100
40 C
to +125
C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
NXP Semiconductors
74HCU04-Q100
Hex inverter
4. Functional diagram
1
1
2
1
1A
1Y
2
3
1
4
3
2A
2Y
4
5
1
6
5
3A
3Y
6
9
1
8
9
4A
4Y
8
11
5A
5Y
10
11
1
10
13
6A
6Y
12
13
1
mna343
12
A
Y
mna045
mna342
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one
inverter)
5. Pinning information
+&84
WHUPLQDO
LQGH[ DUHD
9
&&
$
<
$
9
<
*1'
<
$
$
<
9
&&
$
<
$
<
DDD
+&84
$
<
$
<
$
<
*1'
$
<
$
<
$
<
DDD
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to V
CC
.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
74HCU04_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 31 January 2013
2 of 16
NXP Semiconductors
74HCU04-Q100
Hex inverter
5.1 Pin description
Table 2.
Symbol
1A
1Y
2A
2Y
3A
3Y
GND
4Y
4A
5Y
5A
6Y
6A
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data output
data input
data output
data input
data output
ground (0 V)
data output
data input
data output
data input
data output
data input
supply voltage
6. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level
Input
nA
L
H
Output
nY
H
L
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
SO14, TSSOP14 and
DHVQFN14 packages
[1]
[2]
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
Min
0.5
-
-
-
-
50
65
-
Max
+7.0
20
50
25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
74HCU04_Q100
Product data sheet
Rev. 1 — 31 January 2013
3 of 16
NXP Semiconductors
74HCU04-Q100
Hex inverter
[2]
For SO14 package: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP14 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN14 packages: P
tot
derates linearly with 4.5 mW/K above 60
C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
supply voltage
input voltage
output voltage
ambient temperature
Conditions
Min
2.0
0
0
40
Typ
5.0
-
-
+25
Max
6.0
V
CC
V
CC
+125
Unit
V
V
V
C
9. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol
V
IH
Parameter
HIGH-level
input voltage
Conditions
Min
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
IL
LOW-level
input voltage
V
CC
= 2.0 V
V
CC
= 3.0 V
V
CC
= 5.5 V
V
OH
HIGH-level
V
I
= V
IH
or V
IL
output voltage
I
O
=
20 A;
V
CC
= 2.0 V
I
O
=
20 A;
V
CC
= 4.5 V
I
O
=
20 A;
V
CC
= 6.0 V
V
OL
LOW-level
V
I
= V
IH
or V
IL
output voltage
I
O
= 20
A;
V
CC
= 2.0 V
I
O
= 20
A;
V
CC
= 4.5 V
I
O
= 4.0 mA; V
CC
= 4.5 V
I
O
= 20
A;
V
CC
= 6.0 V
I
O
= 5.2 mA; V
CC
= 6.0 V
I
I
I
CC
C
I
input leakage
current
V
I
= V
CC
or GND;
V
CC
= 6.0 V
1.7
3.6
4.8
-
-
-
1.8
4.0
5.5
25
C
Typ
1.4
2.6
3.4
0.6
1.9
2.6
2.0
4.5
4.32
6.0
5.81
0
0
0.15
0
0.16
-
-
-
-
-
3.5
Max
-
-
-
0.3
0.9
1.2
-
-
-
-
-
0.2
0.5
0.26
0.5
0.26
0.1
2
-
-
-
40 C
to +85
C
Min
1.7
3.6
4.8
-
-
-
1.8
4.0
3.84
5.5
5.34
-
-
-
-
-
-
-
-
-
0.3
0.9
1.2
-
-
-
-
-
0.2
0.5
0.33
0.5
0.33
1.0
20
-
-
-
Max
40 C
to +125
C
Unit
Min
1.7
3.6
4.8
-
-
-
1.8
4.0
3.7
5.5
5.2
-
-
-
-
-
-
20
-
-
-
-
0.3
0.9
1.2
-
-
-
-
-
0.2
0.5
0.4
0.5
0.4
1.0
Max
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
A
A
pF
I
O
=
4.0
mA; V
CC
= 4.5 V 3.98
I
O
=
5.2
mA; V
CC
= 6.0 V 5.48
-
-
-
-
-
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 6.0 V
input
capacitance
74HCU04_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 31 January 2013
4 of 16
NXP Semiconductors
74HCU04-Q100
Hex inverter
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); For test circuit see
Figure 7.
Symbol Parameter
Conditions
25
C
Typ
t
pd
propagation delay
nA to nY; see
Figure 6
V
CC
= 2.0 V; C
L
= 50 pF
V
CC
= 4.5 V; C
L
= 50 pF
V
CC
= 5.0 V; C
L
= 15 pF
V
CC
= 6.0 V; C
L
= 50 pF
t
t
transition time
see
Figure 6
V
CC
= 2.0 V; C
L
= 50 pF
V
CC
= 4.5 V; C
L
= 50 pF
V
CC
= 6.0 V; C
L
= 50 pF
C
PD
power dissipation
capacitance
t
pd
is the same as t
PHL
, t
PLH
.
t
t
is the same as t
THL
, t
TLH
.
C
PD
is used to determine the dynamic power dissipation (P
D
in
W).
P
D
= C
PD
V
CC2
f
i
N +
(C
L
V
CC2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC2
f
o
) = sum of outputs.
[2]
[1]
40 C
to
+85
C
Max
90
18
-
15
95
19
16
40 C
to Unit
+125
C
Max
105
21
-
18
110
22
19
ns
ns
ns
ns
ns
ns
ns
pF
Max
70
14
-
12
75
15
13
-
19
7
5
6
19
7
6
[3]
per inverter; V
I
= GND to V
CC
10
[1]
[2]
[3]
74HCU04_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 31 January 2013
5 of 16
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