电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

CN5830-600BG1521-EXP

产品描述Micro Peripheral IC
产品类别嵌入式处理器和控制器    微控制器和处理器   
文件大小182KB,共2页
制造商Cavium Networks
下载文档 详细参数 全文预览

CN5830-600BG1521-EXP概述

Micro Peripheral IC

CN5830-600BG1521-EXP规格参数

参数名称属性值
厂商名称Cavium Networks
包装说明,
Reach Compliance Codeunknown
Base Number Matches1

文档预览

下载PDF文档
Multi-Core MIPS64 Processors
R
OCTEON Plus CN58XX 4 to 16-Core MIPS64-Based SoCs
Product Brief
The OCTEON
®
Plus CN58XX family of Multi-core MIPS64 processors targets intelligent networking, control plane,
storage, and wireless applications in next-generation equipment from 2 Gbps to full-duplex 10 Gbps (20 Gbps) performance.
The family includes 10 di erent software-compatible parts, with four to sixteen cnMIPS64 cores on a single chip that integrate
next-generation networking I/Os along with the most advanced security and application hardware acceleration to deliver
a 2x – 3x performance, power and real-estate value proposition over alternatives.
®
OVERVIEW
FEATURES
Pin and software compatible with the leading
OCTEON CN38XX/CN36XX family
4-16 cnMIPS™ CPU cores (MIPS64/32 compatible) with MMU
Available in 500 MHz to 800 MHz versions
Enhanced MIPS64 integer (Release2) instruction set
Dual-issue, ve-stage pipeline, optimized latencies
Auto instruction pre-fetching and advanced data
pre-fetching features to minimize memory stalls
BENEFITS
Market-leading performance
Up to 28.8 Billion instructions per second
Leading-edge application performance
-
Up to 30 Mpps 64B IP forwarding
-
Full-duplex up to 10 Gbps for TCP, IPsec, SSL, KASUMI
-
Up to 5 Gbps for Regular Expression
Compression/Decompression
High-performance coherent memory subsystem
Up to 2MB ECC protected 8-way set associative L2
cache with locking, partitioning features for optimal performance
Integrated mainstream 128/144-bit DDR2 memory controller with
ECC, up to DDR2-800
Optional, additional, low-latency 2x18-bit or 4x9-bit RLDRAM2
for content based processing, meta-data and TCAM connectivity
Packet I/O processing, QoS, TCP Acceleration
Support for IPsec, SSL, SRTP, WLAN and UMTS/LTE
security (includes DES, 3DES, AES-GCM, AES up to 256,
SHA1, SHA-2 up to SHA-512, RSA up to 8192, DH, KASUMI)
Regular Expression, Compression/Decompression
Up to 2 sets of I/Os - each con gurable as 4x
10/100/1000 Ethernet MACs (RGMII) or SPI-4.2
Integrated 64-bit, 133 MHz PCI-X host or slave
Double L1/L2 caches and up to 3x Interconnect
bandwidth along with 1 GHz Core delivers up to 2x
performance over OCTEON CN38XX
Sophisticated hardware based QoS support
Queuing, scheduling
Very low latency for real-time tra c
Integrated coprocessors for application acceleration
Reduced BOM cost with essential interfaces for
standalone Routers/Appliances, Line-card and
Services-card applications
Flexible architecture allows host and coprocessor
Implementations
Industry-standard programming model without any need
for Proprietary Tools or Micro-coding
Fully software compatible with OCTEON CN31XX and
CN30XX to deliver 1- 16 CPU scalability
2x – 3x advantage over alternative system architectures in
performance and power for L4-L7 data and security
services
2x performance/watt over OCTEON CN38XX
Integrated high-performance networking interfaces
Comprehensive development environment with Linux,
VxWorks, OSE and C/C++ support
Optimized power consumption: 15W – 40W
Package: 1521 FCBGA
OCTEON
®
Plus CN58XX
- Block Diagram
Optional 2x18-bit
RLDRAM2
SPI 4.2
or
4x RGMII
Packet
Interface
Secure
Vault
32x RegEx
Engines
Hyper Access Low Latency
Memory Controller
Packet
Packet
Boot/flash
GPIO
2xUART
Scheduler/
Sync. Order
Security
MIPS64 r2
Integer Core
32K Icache
Misc I/O
PCI-X
TCP Unit
I/O Bridge
Compress
/Decomp
64-bit,
133MHz
4 to 16
cnMIPS64
cores
Security
MIPS64 r2
Integer Core
32K Icache
16K Dcache
2K Write Buffer
Packet
Input
16K Dcache
2K Write Buffer
Coherent, Low Latency
Interconnect
2 MB
L2 Cache
2315 N. First Street
San Jose, CA 95131
T
408-943-7100
F
408-577-1992
E
sales@cavium.com
www.cavium.com
SPI 4.2
or
4x RGMII
Packet
Interface
I/O Bus
Packet
Output
Hyper Access
Memory Controller
DDR2 up to
800 MHz
72 or 144-bit wide
用DSP进行mp3解压缩的算法原程序
33294...
西点 DSP 与 ARM 处理器
ce下,如何获取输入框的光标位置
在一个对话框,有一个编辑框和一个按钮。要求:按下按钮后,在编辑框的光标所在位置,插入一个字符串。 实现的代码: 1)输入框丢失焦点的事件的响应:保存编辑框的光标所在的字符位置nCharIn ......
vernusian 嵌入式系统
【信号处理】介绍基于DSP和FPGA的专业级音频处理开发板资料
采用TMS320C5409和Cyclone EP1C3T144C8 FPGA、作为主处理器、协处理器。采用24bit高精度音频专用AD/DA转换芯片,特别适合应用于电台、录音室等专业级音频处理设备开发。 该开发板是面向专业级 ......
hangsky FPGA/CPLD
【GD32450I-EVAL】UART
这块板子的串口比较粗暴,是直接引出至232,使用的max3232进行转接的。 504168 使用的板载串口为USART0,从原理图可以看到接的是PA9和PA10。 (一)时钟 串口初始化首先要使能时钟: ......
tinnu GD32 MCU
wince 法文键盘
我看wince资料说支持法文键盘。法文键盘的LANGID:040C 可我没有找到这个语言的代码。希望知道帮忙说下。...
wangshujun 嵌入式系统
9b96的safertos问题求助
我把safertos_demo例程的.bin文件烧到自己做的板子里,感觉没有运行。里面的闪灯任务就是闪网口上的灯(ROM_GPIOPinWrite(GPIO_PORTF_BASE, GPIO_PIN_3, GPIO_PIN_3);),按理说应该闪灯。在线运 ......
radarbq 微控制器 MCU

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 1910  897  2866  1588  1825  17  33  21  25  37 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved